Senior Memory Controller Engineer

1 week ago

Austin, Texas, United States Mastech Digital Full time

Position: Custom Memory Controller Designer / RTL Engineer

Location: Austin (Preferred), Open for San Jose/San Diego (Hybrid 3 days onsite)

  • Essential Qualifications: In-depth knowledge of memory controller micro-architecture with 3-5 years of current experience.
  • Proficiency in various memory technologies such as LPDDR4/5 and HBM.
  • Familiarity with JEDEC memory standards is advantageous.
  • Understanding of AES, ECC, and RAS features is preferred.
  • Strong RTL Design skills are essential with relevant experience.

Role Overview:

As a Senior Designer specializing in custom memory controller micro-architecture, you will play a pivotal role in the development of advanced memory controllers for LPDDR5 and LP technologies. This position involves collaboration with system architects, verification teams, and design implementation teams. You will be responsible for leading and managing critical RTL design tasks, focusing on performance and power optimization, as well as addressing logic debugging and timing closure challenges. A solid engineering foundation coupled with extensive RTL design experience is crucial for success in this role.

Key Responsibilities:

  • Oversee the timely development and debugging of innovative features for custom memory controllers.
  • Engage in SOC IP delivery while ensuring all necessary checks are completed.
  • Conduct timing debugging and closure activities.
  • Manage LINT and CDC flows along with comprehensive analysis.
  • Utilize power artist flow for power analysis.
  • Handle ECO flows effectively.
  • Collaborate with the verification team to ensure design functionality and correctness.
  • Work closely with implementation teams to meet timing and area requirements.
  • Deliver high-quality RTL on schedule while achieving performance, power, and area (PPA) goals.
  • Partner with performance and power teams to meet established objectives.
  • Coordinate with physical design and CAD teams to resolve implementation details.

Preferred Qualifications:

  • PhD, Master's, or Bachelor's Degree in Computer Engineering with over 10 years of relevant experience.
  • Proven track record in leading RTL design for various sub-blocks of custom memory controllers.
  • Demonstrated success in architectural through RTL design for high-performance digital systems.
  • Expertise in Verilog and a comprehensive understanding of ASIC design flows, including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, and ECO.
  • Strong knowledge of memory controller micro-architecture.
  • Familiarity with memory technologies such as LPDDR4/5 and HBM.
  • Awareness of JEDEC memory standards is a plus.
  • Knowledge of AES, ECC, and RAS features is beneficial.
  • Excellent communication and interpersonal skills, with the ability to thrive in a dynamic, global team environment.
  • Experience with scripting languages such as Perl or Python.
  • A passion for logic design, characterized by energy and curiosity.
  • Strong written and verbal communication skills.

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