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Senior Memory Controller Engineer
2 months ago
Position: Custom Memory Controller Designer / RTL Engineer
Location: Austin (Preferred) Open for San Jose/San Diego (Hybrid 3 days onsite)
Essential Qualifications:
- Proficient understanding of memory controller micro-architecture with a minimum of 3-5 years of relevant experience.
- Experience with various memory technologies such as LPDDR4/5 and HBM.
- Familiarity with JEDEC memory standards is advantageous.
- Knowledge of AES, ECC, and RAS features is preferred.
- Strong RTL design skills are essential, with current experience in the field.
Role Overview:
As a Senior Designer specializing in custom memory controller micro-architecture, you will engage in the development of cutting-edge memory controllers for LPDDR5 and LP technologies. This role involves collaboration with system architects, verification teams, and design implementation teams. You will take ownership of critical RTL design tasks, focusing on performance and power optimization, while also addressing logic debugging and timing closure challenges. A solid engineering foundation and substantial RTL design experience are crucial for success in this position.
Key Responsibilities:
- Lead the development and debugging of innovative features for custom memory controllers.
- Oversee SOC IP delivery, ensuring all quality checks are met.
- Engage in timing debug and closure processes.
- Conduct LINT and CDC flows and analyses.
- Implement power artist flows and perform power analyses.
- Manage ECO flows effectively.
- Collaborate with the verification team to ensure design functionality and correctness.
- Work closely with implementation teams to meet timing and area requirements.
- Deliver high-quality RTL designs on schedule, achieving performance, power, and area (PPA) goals.
- Partner with performance and power teams to meet established targets.
- Coordinate with physical design and CAD teams to resolve implementation details.
Preferred Candidate Profile:
- PhD, Master's, or Bachelor's Degree in Computer Engineering with over 10 years of experience.
- Proven track record in leading RTL design for various sub-blocks of custom memory controllers.
- Demonstrated success in architectural through RTL design experience on high-performance digital designs.
- Expertise in Verilog and a comprehensive understanding of ASIC design flows, including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, and ECO.
- Strong communication and interpersonal skills, with the ability to thrive in a dynamic, global team environment.
- Experience with scripting languages such as Perl or Python.
- A passionate and curious approach to logic design.
- Excellent written and verbal communication skills.
