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Senior Memory Controller Engineer

2 months ago

Austin, Texas, United States Mastech Digital Full time

Position: Senior Memory Controller Engineer

Location: Austin (Preferred), San Jose/San Diego (Hybrid 3 days onsite)

Essential Qualifications:

  • Proficient understanding of memory controller micro-architecture with 3-5 years of relevant experience.
  • Experience with various memory technologies such as LPDDR4/5 and HBM.
  • Familiarity with JEDEC memory standards is advantageous.
  • Knowledge of AES, ECC, and RAS features is preferred.
  • Strong RTL design skills are essential.

Role Overview:

As a Senior Memory Controller Engineer, you will play a pivotal role in the micro-architecture development of custom memory controllers for LPDDR5 and LP. Your responsibilities will include collaborating with system architects, verification teams, and design implementation teams. You will lead the RTL design efforts, focusing on performance and power optimization, as well as logic debugging and timing closure.

Key Responsibilities:

  • Oversee the development and debugging of new features for custom memory controllers.
  • Ensure successful SOC IP delivery with comprehensive sanity checks.
  • Engage in timing debug and closure processes.
  • Conduct LINT and CDC flows and analyses.
  • Utilize power artist flow for power analysis.
  • Manage ECO flows effectively.
  • Collaborate with the verification team to ensure design functionality and correctness.
  • Work closely with implementation teams to meet timing and area objectives.
  • Deliver high-quality RTL on schedule while achieving PPA goals.
  • Coordinate with performance and power teams to meet established targets.
  • Partner with physical design and CAD teams to address implementation details.

Preferred Qualifications:

  • PhD, Master's, or Bachelor's Degree in Computer Engineering with over 10 years of experience.
  • Proven track record in leading RTL design for various sub-blocks of custom memory controllers.
  • Demonstrated success in architectural through RTL design for high-performance digital systems.
  • Expertise in Verilog and a comprehensive understanding of ASIC design flow, including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, and ECO.
  • Strong communication and interpersonal skills, with the ability to thrive in a dynamic, global team environment.
  • Experience with scripting languages such as Perl or Python.
  • A passion for logic design, characterized by energy and curiosity.
  • Excellent written and verbal communication skills.