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Senior Memory Controller Engineer
2 months ago
Position: Senior Memory Controller Designer/RTL Engineer
Location: Flexible (Hybrid model available)
- Essential Qualifications: Proven expertise in memory controller micro-architecture with a minimum of 3-5 years of relevant experience.
- Familiarity with various memory technologies, including LPDDR4/5 and HBM.
- Understanding of JEDEC memory standards is advantageous.
- Knowledge of AES, ECC, and RAS features is preferred.
- Strong RTL design skills are essential.
Role Overview:
As a Senior Designer specializing in custom memory controller micro-architecture, you will take charge of the development of innovative memory controller solutions for LPDDR5 and LP. This role involves collaboration with system architects, verification teams, and design implementation units. You will be responsible for leading the RTL design, optimizing performance and power, and addressing logic debugging and timing closure challenges. A solid engineering foundation coupled with extensive RTL design experience is crucial for success in this position.
Key Responsibilities:
- Lead the timely development and debugging of new features for custom memory controllers.
- Oversee SOC IP delivery, ensuring all quality checks are met.
- Engage in timing debug and closure processes.
- Conduct LINT and CDC flows and analyses.
- Implement power artist flows and perform power analysis.
- Manage ECO flows effectively.
- Collaborate with the verification team to ensure design functionality and correctness.
- Work closely with implementation teams to meet timing and area requirements.
- Deliver high-quality RTL on schedule while achieving performance, power, and area (PPA) goals.
- Partner with performance and power teams to meet established objectives.
- Coordinate with physical design and CAD teams to resolve implementation-level details.
Preferred Qualifications:
- PhD, Master's, or Bachelor's Degree in Computer Engineering with over 10 years of experience.
- Strong background in leading RTL design for various sub-blocks of custom memory controllers.
- Demonstrated success in architectural through RTL design experience for high-performance digital designs.
- Expertise in Verilog and a comprehensive understanding of the ASIC design flow, including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, and ECO.
- Knowledge of memory controller micro-architecture.
- Familiarity with different memory technologies such as LPDDR4/5 and HBM.
- Understanding of JEDEC memory standards is preferred.
- Knowledge of AES, ECC, and RAS features is advantageous.
- Strong communication and interpersonal skills, with the ability to thrive in a dynamic, global team environment.
- Experience with scripting languages such as Perl or Python.
- A passion for logic design, characterized by energy and curiosity.
- Excellent written and verbal communication skills.