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Lead Architect: PCIe Endpoint

2 months ago

Portland, Oregon, United States Ampere Full time
About the Role

We are seeking an experienced PCIe endpoint architect to join our team at Ampere. As a key member of our architecture team, you will be responsible for defining enhancements and new sub-components for our custom interconnect IP to meet the requirements of our future AI accelerator product roadmap.

This is an exciting opportunity to be at the forefront of new architecture developments in this strategically critical project. You will work closely with our team to design and develop innovative solutions that meet the needs of our customers.

Key Responsibilities
  • Own the architecture of the product from initial path-finding to production, and support it through execution to product tape-out, and through post-si validation to production.
  • Work with the broader AI accelerator team to understand the target workloads and compute and memory needs of the product and translate this into requirements of the interconnect.
  • Balance features, performance, power, and area to create a solution with high value and optimal use of development and physical resources.
  • Work with the performance modeling team to evaluate critical metrics such as bandwidth and latency to ensure the interconnect is optimized for the target workloads.
  • Use data-based analysis to study trade-offs that include protocol efficiency, bandwidth, protocol efficiency, and software usage models to inform or make critical product and IP decisions.
Requirements
  • BS degree in Electrical Engineering, Computer Engineering, or Computer Science and 12 years of experience; or MS degree and 8 years of experience; or PhD degree and 5 years of experience.
  • Experience architecting and/or designing high-performance, high-bandwidth device interconnects, along with modern methods of device abstraction and security (SR-IOV, RCiEP).
  • Deep understanding of memory usage protocols; knowledge of modern memory models.
  • Experience with cache architecture and/or design.
  • Deep understanding of software usage models for adaptive learning models.
  • Understanding of ordering, in-out dependencies, and deadlocks.
  • Understanding of pipelines, dependencies, parallelism, ordering, and deadlocks.
  • Experience with chiplet-based SoC architecture including AI accelerators or GPU architectures.
  • Knowledge and understanding of PCIe and CXL with experience with Linux architecture from a device viewpoint.
  • Ability to learn and adapt, one of the foundational principles of Ampere.
  • Must be self-driven, curious, organized and comfortable with ambiguity.
  • Great communication skills, comfortable with reaching out and asking questions, and brainstorming with peers.
What We Offer

At Ampere, we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus, equity, and comprehensive benefits.

The full base pay range for this role is between $163,100 and $271,900, except in the San Francisco Bay Area where the range is between $171,800 and $286,300.

We offer an annual bonus program tied to internal company goals and annual meritocratic equity awards that enable our employees to participate in the success of the company.

Our benefits include health, wellness, and financial programs that support employees through every stage of life, with full benefits eligibility at 20 hours per week.