ASIC Design Verification Engineer

4 days ago


San Jose, California, United States Cisco Full time
Job Description

Cisco is seeking a highly skilled ASIC Design Verification Engineer to join their Silicon One development organization in San Jose, CA.

Key Responsibilities:
  1. Maintain and enhance existing DV environments to ensure seamless verification of complex ASICs.
  2. Design and develop testbenches for new blocks, incorporating scoreboard, agents, sequencers, and monitors.
  3. Create test plans, write test cases, debug regression failures, and drive module verification closure.
  4. Implement and review code and functional coverage to ensure complete verification.
Requirements:
  • Bachelor's or Master's degree and 8 years of relevant experience required; prior expertise with System Verilog and UVM methodology.
  • Proven track record in verifying complex blocks, clusters, and top-level SoCs.
  • Hands-on experience with building testbenches from scratch and System Verilog constraints, structures, and classes.
  • Strong understanding of functional coverage and constrained random DV environments.
  • Proficiency in scripting languages: Perl and/or Python.
Preferred Qualifications:
  • Domain expertise on one or more protocols: PCIe, CXL, Ethernet, AHB/AXI, DDR, MMU.
  • Experience with Veloce/HAPS and formal verification tools.
What We Offer:
  • A competitive estimated salary range of $140,000 - $180,000 per year.
  • The opportunity to work on cutting-edge projects with a dynamic team.
  • A collaborative environment that fosters innovation and growth.


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