Senior ASIC Design Verification Lead
4 days ago
Cisco's Core Hardware Business Unit is seeking a highly motivated Senior ASIC Design Verification Lead to engage in new development of our UCS family. This role requires hands-on experience in RTL verification, in-depth knowledge of SoC development cycles, and best industry practices.
Job SummaryWe are looking for an experienced Senior Verification engineer/lead to design and verify complex ASICs. The successful candidate will have a proven track record of success in high-performance/high-volume semiconductor markets.
Key Responsibilities- Architect block, cluster, and top-level DV environment infrastructure.
- Create DV infrastructure from scratch for block, cluster, and top-level environments.
- Maintain existing DV environments and enhance them.
- Ensure complete verification coverage through implementation and review of code and functional coverage.
- Work closely with designers.
- Support tests done with emulation.
- Work closely with software teams and debug issues found during firmware development.
- 10+ years of ASIC design verification experience with a Bachelor's or Master's degree.
- Prior experience with ASIC verification using UVM/System Verilog.
- Prior experience in verifying complex blocks, clusters, and top-level designs for SoCs.
- Prior experience building test benches from scratch, hands-on experience with System Verilog constraints, structures, and classes.
- Prior experience with cross-functional teams and the drive to learn and grow.
- Prior experience on one or more protocols - PCIe, Ethernet, RDMA, TCP.
- Lead a team of engineers to complete verification of a complex block, cluster, or chip-level design.
- Lead verification for a complete SOC or ASIC.
- Prior experience with forwarding logic/Parsers/P4.
- Formal verification (IEV/VC formal) knowledge.
The estimated salary for this position is $140,000-$170,000 per year, depending on experience. Cisco offers a comprehensive benefits package, including medical, dental, and vision insurance, 401(k) matching, and paid time off.
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