Senior ASIC Design Engineering Manager
1 day ago
Cisco Systems, Inc. is seeking a Senior ASIC Design Engineering Manager to lead the design and verification of application-specific integrated circuits (ASICs) for our core Switching, Routing, and Wireless products.
As a key member of our team, you will oversee chip-level PNR activities, ensuring performance, power, and area specifications are met. You will also coordinate cross-functional teams, guide design methodologies, and address technical challenges throughout the development process.
The ideal candidate will have 10+ years of hands-on experience in ASIC implementation and Physical verification, with expertise in physical verification tools such as Cadence, Innovus, Synopsys IC Compiler, or Fusion Compiler. You will also have scripting experience in TCL, Perl, or Makefile to streamline and automate workflows.
This role offers an estimated salary of $250,000 - $350,000 per annum, depending on location and experience. Benefits include quality medical, dental, and vision insurance, a 401(k) plan with a Cisco matching contribution, short and long-term disability coverage, basic life insurance, and numerous wellbeing offerings.
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The successful candidate will be responsible for:
- Leading chip-level PNR activities, including floor planning, bump and RDL planning, power grid design, clock planning, routing, and timing closure
- Performing full chip DRC/LVS/ERC/ANT checks, reviewing and debugging issues, providing solutions, and ensuring signoff clean results
- Coordinating with block and TOP level physical implementation, IP development teams, and resolving PV issues and addressing them to proper owners
- Deploying and improving physical verification flows and methodologies, developing custom checks as needed for verification robustness
- Guiding and mentoring a team of physical design engineers on project-level backend implementation and partnering closely with frontend, integration, and verification teams
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