Parallel Processing Systems Engineer

7 days ago


Santa Clara, California, United States Apple Full time
Job Summary

We are seeking a highly skilled ASIC Design Engineer to join our team at Apple. As a key member of our memory systems team, you will be responsible for designing and developing high-performance cache architectures for our next-generation parallel processing systems.

Key Responsibilities
  • Participate in the development of cache microarchitectures from specifications and model analysis.
  • Explore architecture trade-offs in system performance, area, and power consumption with the performance analysis team.
  • Develop and debug RTL designs of different sections of the cache.
  • Collaborate with the physical design team to close timing of the cache.
Requirements
  • Experience in developing memory systems.
  • Strong background in RTL/micro-architecture definition.
  • Knowledge of PPA (performance/power/area) analysis.
  • Experience with cache design, including understanding of different memory organizations and trade-offs.
  • Knowledge of memory subsystems and dram controllers.
  • Hands-on experience with multi-processor cache coherence protocols.
Education and Experience

Bachelor's Degree + 10 years of experience in ASIC design and development.

Additional Requirements
  • Strong understanding of Apple's technology and products.
  • Excellent communication and collaboration skills.
  • Ability to work in a fast-paced environment and meet deadlines.
Compensation and Benefits

At Apple, we offer a competitive compensation package, including a base salary range of $175,800 to $312,200, depending on skills, qualifications, experience, and location. Additionally, you will be eligible for discretionary bonuses, commission payments, and relocation assistance. Our comprehensive benefits package includes medical and dental coverage, retirement benefits, and a range of discounted products and services.



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