Logic Validation Engineer

1 week ago

San Jose, California, United States Intel Full time
Job Details:

Job Description:

The Foundational Security team (FST) is seeking a skilled logic validation engineer to work on a scalable IP design. The successful candidate will be responsible for validating new IP roadmap features as part of FST's HW IP development of HW security for various market segments across Intel.

As a member of the team, the candidate will drive scalable IP development while ensuring the Design Integration and SOC delivery is a fully automated solution. The candidate will work closely with other verification engineers, RTL design engineers, micro-architects, and other team members to determine the proper implementation strategy for new designs, ensure quality of design, and develop test-plans, verification environment, and drive delivery to SoC.

The candidate will have the opportunity to learn and contribute towards making Intel Hardware more secure. Excellent communication and organization skills are critical, along with teamwork, and must demonstrate strong technical skills, along with having a passion for design or validation.

Key Responsibilities:

  • Validate new IP roadmap features
  • Drive scalable IP development
  • Ensure Design Integration and SOC delivery is automated
  • Work closely with verification engineers, RTL design engineers, micro-architects, and other team members
  • Develop test-plans, verification environment, and drive delivery to SoC

Requirements:

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent
  • 0-2 years of relevant logic design/pre-silicon verification experience with multiple project cycles
  • Advanced English level
  • Costa Rican unrestricted work permit
  • 0-2 years of logic design/pre-silicon verification experience with various tools and methodologies including System Verilog, RTL simulators, Testbench development, and VLSI or Structural and Physical design flow/methodology experience

Preferred Qualifications:

  • RTL model build
  • Power-aware simulation
  • Coverage-based random constraint simulation
  • Capable in developing testplans, tests and verification environment based on High Level Architecture specifications
  • Power management, IOSF, AHB, PCI express or any industry standard BUS protocol experience a plus
  • OVM / UVM
  • Scripting (Python/Perl/Shell)
  • Interactive debugger

Job Type: Experienced Hire

Shift: Shift 1 (Costa Rica)

Primary Location: Costa Rica, San Jose

Additional Locations:

Business Group: In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel's products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore's Law and groundbreaking innovations. DEG is Intel's engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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