Senior Low Power Logic Design Engineer
5 days ago
Job Summary
Apple is seeking a highly skilled Senior Low Power Logic Design Engineer to join our Wireless SOC organization. As a key member of our team, you will be responsible for designing power management logics for complex wireless communication SoCs.
Key Responsibilities
- Define and write specifications to cover SOC power management features to meet product requirements
- Implement power management logic
- Work with Design Verification, FPGA, and other teams to verify power management logics
- Collaborate with the Power team for power analysis work
- Perform post-silicon power management feature debug
- Support the Power team in performing power correlation
Requirements
- Proven track record in power/clock management logic design
- Proficiency in Verilog language
- SoC level power management logic verification and debug experience
- Deep understanding of ASIC low power design techniques
- Knowledge of CDC, RDC, and UPF and its VCLP checker
- Strong problem-solving skills
- Proficiency in scripting languages, e.g., Unix shell, Perl, or Python
- SoC top-level integration experience is a plus
- SW team support experience is a plus
- System architecture knowledge is a plus
- Post-silicon debug experience is a plus
Education & Experience
- BS and 10+ years of relevant industry experience
Additional Requirements
- Apple is an equal opportunity employer that is committed to inclusion and diversity
- We take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities
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