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Validation Engineering Specialist
2 months ago
Verification Design Engineer
- Location: Flexible / Remote
- Duration: 6 months + (potential extension)
- Essential Skills: UVM, System Verilog, Test Bench Development, SystemC (preferred), proficient in C/C++
We are excited to announce an opportunity for a skilled Verification Design Engineer to become a vital part of our team at Intelliswift Software. This position focuses on the forefront of technology in the realm of design verification and validation.
The ideal candidate will possess a robust understanding of UVM and System Verilog, complemented by hands-on experience in test bench development and SystemC. Proficiency in C/C++ programming is essential for success in this role.
If you are dedicated to the field of verification engineering and thrive in a collaborative, innovative environment, we encourage you to consider this opportunity to advance your career.
