Senior Logic Design Engineer, Cache Coherent Interconnects
3 days ago
We are seeking a highly skilled Senior Logic Design Engineer to join our CPU Logic Design Team. As a member of this team, you will be responsible for designing CPU on-chip and off-chip interconnect networks, focusing on micro-architectural definition, RTL coding, logic debug, synthesis, and timing closure.
Key Responsibilities- Design and develop high-performance and low-power RTL for CPU interconnect networks
- Collaborate with the verification team to ensure correctness of the interconnect network
- Work with the implementation team to achieve timing, area, performance, and power goals
- Assist with timing closure of super units
- Master's Degree in Electrical Engineering, Computer Engineering, or Computer Science
- 8+ years of experience in processor or other related high-performance semiconductor designs
- Verilog expertise and deep understanding of ASIC design flow
- Strong communication and interpersonal skills
NVIDIA is a leader in the technology industry, known for its innovative products and commitment to excellence. We offer a dynamic and global work environment, with opportunities for growth and development.
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Santa Clara, California, United States NVIDIA Corporation Full timeJob SummaryNVIDIA Corporation is seeking a highly skilled Senior Logic Design Engineer to join our CPU Logic Design Team. As a member of this team, you will be responsible for designing CPU on-chip and off-chip interconnect networks, MP coherency, and last-level and system caches.Key ResponsibilitiesDesign and develop high-performance and low-power RTL for...
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Santa Clara, California, United States NVIDIA Full timeJoin NVIDIA's CPU Logic Design Team as a Senior Logic Design Engineer and contribute to the design of CPU on-chip and off-chip interconnect networks, MP coherency, and last-level and system caches. As a member of our team, you will be responsible for micro-architectural definition, RTL coding, logic debug, synthesis, and timing closure, supporting...
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Senior Logic Design Engineer
2 weeks ago
Santa Clara, California, United States NVIDIA Full timeJob Title: Senior Logic Design Engineer - Physical DesignWe are seeking a highly skilled Senior Logic Design Engineer with a background in Physical Design to join our CPU Logic Design Team. As a member of this team, you will be responsible for designing CPU on-chip interconnect networks and last-level caches, working closely with the physical design team on...
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Senior Logic Design Engineer
7 days ago
Santa Clara, California, United States NVIDIA Full timeJob Title: Senior Logic Design EngineerWe are seeking a highly skilled Senior Logic Design Engineer to join our CPU Logic Design Team. As a member of this team, you will be responsible for designing CPU on-chip and off-chip interconnect networks, MP coherency, and last-level and system caches.Key Responsibilities:Design and develop high-performance and...
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Santa Clara, California, United States Ampere Computing Full timeAbout the RoleAmpere Computing is seeking a highly skilled Senior Principal Engineer to join our team in the role of Cache Coherency Subsystem Verification. As a key member of our design verification team, you will be responsible for leading the verification efforts of our server-class microprocessor-based Coherent Mesh interconnect subsystem.Key...
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Santa Clara, California, United States Ampere Computing Full timeAbout the RoleAmpere Computing is seeking a highly skilled Senior Principal Engineer to join our team in the role of Cache Coherency Subsystem Verification. As a key member of our design verification team, you will be responsible for leading the verification efforts of our server-class microprocessor-based Coherent Mesh interconnect subsystem.Key...
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Senior Logic Design Engineer
8 hours ago
Santa Clara, California, United States NVIDIA Full timeSenior Logic Design EngineerWe are seeking a highly skilled Senior Logic Design Engineer to join our CPU Logic Design Team. As a member of this team, you will be responsible for designing CPU on-chip and off-chip interconnect networks, MP coherency, and last-level and system caches.This is a unique opportunity to have a real impact in a dynamic,...
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Santa Clara, California, United States Ampere Computing Full timeAbout the RoleAmpere Computing is seeking a highly skilled Senior Principal Engineer to join our team in the Cache Coherency Subsystem Verification department. As a key member of our team, you will be responsible for leading the verification efforts of our server-class microprocessor-based Coherent Mesh interconnect subsystem.Key ResponsibilitiesDevelop and...
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Senior Logic Design Engineer
4 weeks ago
Santa Clara, California, United States NVIDIA Full timeAbout the RoleWe are seeking a highly skilled Senior Logic Design Engineer - Physical Design to join our CPU Logic Design Team. As a member of this team, you will be responsible for designing CPU on-chip interconnect networks and last-level caches, working closely with the physical design team on implementation, synthesis, and timing closure. You will also...
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Senior Design Engineer
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Santa Clara, California, United States NVIDIA Full timeNVIDIA Senior Design Engineer - Coherent High Speed InterconnectNVIDIA is seeking a highly skilled Senior Design Engineer to join our Coherent High Speed Interconnect team. As a key member of our team, you will be responsible for designing and developing state-of-the-art high speed coherent interconnects for our mobile SoCs and GPUs.Key...
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Santa Clara, California, United States Ampere Full timeAbout the RoleWe are seeking a highly skilled Senior Principal Engineer to lead the verification of our server-class microprocessor-based Coherent Mesh interconnect subsystem.As a key member of our Design Verification team, you will be responsible for ensuring the functional correctness and performance of our CPUs.You will work closely with other teams to...
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Logic Design Specialist
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Santa Clara, California, United States NVIDIA Full timeAbout the RoleWe are seeking a highly skilled Senior Logic Design Engineer - Physical Design to join our CPU Logic Design Team. As a member of this team, you will be responsible for designing CPU on-chip interconnect networks and last-level caches, working closely with the physical design team on implementation, synthesis, and timing closure. You will also...
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CPU Design Engineer
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ASIC Design Engineer
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Santa Clara, California, United States Apple Inc. Full timeJob SummaryWe are seeking a highly skilled ASIC Design Engineer to join our team at Apple Inc. as a Memory Cache Controller Design Expert. In this role, you will be responsible for crafting special purpose cache and controller designs that are part of the SOC memory hierarchy.Key ResponsibilitiesParticipate in cache micro-architecture development from...
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Santa Clara, California, United States NVIDIA Full timeAbout the RoleNVIDIA is seeking a highly skilled Senior Design Engineer to join our Coherent High Speed Interconnect team. As a key member of this team, you will be responsible for designing and developing cutting-edge high speed coherent interconnects for our mobile SoCs and GPUs.Key ResponsibilitiesCollaborate with architects, external partners, software...
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Santa Clara, California, United States NVIDIA Full timeAbout the RoleNVIDIA is seeking a highly skilled Senior Design Engineer to join our Coherent High Speed Interconnect team. As a pioneer in visual computing, NVIDIA has revolutionized the field with the invention of the GPU, enabling applications in video games, movie production, product design, medical diagnosis, and scientific research.We are now at the...
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Senior ASIC Design Engineer
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Santa Clara, California, United States Apple Full timeJob Title: Senior ASIC Design EngineerAt Apple, we're pushing the boundaries of innovation in mobile processing systems. Our high-bandwidth multi-client memory subsystems are revolutionizing the industry. As we increase levels of parallelism, bandwidth, and capacity, we're presented with design challenges that require expertise in crafting special purpose...
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CPU Cache RTL Architect
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