Senior ASIC Design Engineer

2 days ago


Santa Clara, California, United States Apple Full time
Job Title: Senior ASIC Design Engineer

At Apple, we're pushing the boundaries of innovation in mobile processing systems. Our high-bandwidth multi-client memory subsystems are revolutionizing the industry. As we increase levels of parallelism, bandwidth, and capacity, we're presented with design challenges that require expertise in crafting special purpose cache and controller systems.

Key Responsibilities:
  • Participate in cache micro-architecture development from specifications and model analysis.
  • Explore architecture trade-offs in system performance, area, and power consumption with the performance analysis team.
  • Develop and debug RTL design of different sections of the cache.
  • Work with the physical design team to close timing of the cache.
Requirements:
  • Development of memory systems.
  • Experience in RTL/micro-architecture definition.
  • Experience in PPA (performance/power/area) analysis.
  • Knowledge of coherent memory system or interconnect architectures.
  • Strong cache design background, including good understanding of different memory organizations and trade-offs.
  • Knowledge of memory subsystem and dram controller.
  • Hands-on experience with multi-processor cache coherence protocols.
What We Offer:
  • Comprehensive medical and dental coverage.
  • Retirement benefits.
  • Discounted products and free services.
  • Reimbursement for certain educational expenses.
  • Discretionary bonuses or commission payments.
  • Relocation assistance.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.



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