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ASIC Design Engineer

2 months ago

Santa Clara, California, United States Apple Inc. Full time
Job Summary

We are seeking a highly skilled ASIC Design Engineer to join our team at Apple Inc. as a Memory Cache Controller Design Expert. In this role, you will be responsible for crafting special purpose cache and controller designs that are part of the SOC memory hierarchy.

Key Responsibilities
  • Participate in cache micro-architecture development from specifications found from architecture guidelines and model analysis.
  • Explore architecture trade-offs in system performance, area, and power consumption along with the performance analysis team.
  • Develop and debug RTL design of different sections of the cache.
  • Work with physical design teams to close timing of the cache.
Requirements
  • Development of memory systems.
  • Experience in PPA (performance/power/area) analysis.
  • Knowledge of dedicated coherent memory systems or interconnect architectures.
  • Strong cache design background, including a good understanding of different memory organizations and trade-offs.
  • Knowledge of dedicated memory subsystems and DRAM controllers.
  • Hands-on experience with multi-processor cache coherence protocols.
Preferred Qualifications
  • Bachelor's Degree + 3 years of experience.
What We Offer
  • Comprehensive medical and dental coverage.
  • Retirement benefits.
  • A range of discounted products and free services.
  • Reimbursement for certain educational expenses.
  • Discretionary bonuses or commission payments.
  • Relocation assistance.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.