ASIC STA Engineer

4 weeks ago


San Jose, California, United States Cisco Full time
About the Role

Cisco is seeking a highly skilled ASIC STA Engineer to join our team in delivering cutting-edge silicon, optics, and hardware platforms for our core Switching, Routing, and Wireless products.

Key Responsibilities
  • Closing timing at block, sub-chip, and full-chip levels
  • Performing quality checks such as setup, hold, transition, and noise
  • Managing ECO tasks and advising the Physical Design team on best practices
  • Developing methodologies, guidelines, and checklists to streamline STA work
Requirements
  • Bachelor's degree in electrical or computer engineering (or other equivalent field) with 7+ years of related work experience
  • Experience with Integration for STA, including Hyperscale and hierarchical analysis with parasitic stitching, IO budgeting, and flat parasitic extraction
  • Timing closure with various timing ECO including transition, setup, hold, noise, xtalk, and power recovery
  • Familiarity with various on-chip variation including AOCV, POCV and voltage, temperature, aging-based timing derates
  • Scripting skills in TCL, Perl, or Python
Preferred Qualifications
  • Master's Degree in electrical or computer engineering (or other equivalent field) with 5+ years of related work experience
  • Experience with Synopsys DC/DCG/FC, Synopsys Formality and Cadence LEC, Synopsys Star-RCXT, Cadence Quantus, Synopsys Primetime/PTPX/Tweaker/PrimeClosure, and Cadence Tempus


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