Senior Staff ASIC Design Engineer

17 hours ago

San Jose, California, United States Samsung Semiconductor Full time
Job Title: Senior Staff ASIC Design Engineer

We are seeking a highly skilled Senior Staff ASIC Design Engineer to join our dynamic engineering team at Samsung Semiconductor. As a key member of our Advanced Processor Lab, you will be responsible for designing and implementing high-performance CPU cores and related IPs.

Key Responsibilities:
  • Develop and implement RTL for CPU cores and related IPs
  • Work closely with frontend and backend teams to ensure optimal design closure, including timing, area, and power optimizations
  • Collaborate on the development of micro-architecture specifications for CPU components
  • Conduct synthesis, STA (Static Timing Analysis), DFT (Design for Test), and other validation tasks as required
  • Perform backend tasks, including place and route (PR), physical design closure, and tape out
  • Ensure the design meets performance, area, power, and reliability targets
  • Participate in the design and verification of complex digital IP blocks, integrating them into the overall SoC
  • Interface with verification, DFT, and software teams to resolve design issues and ensure smooth handoffs between design phases
  • Work with prototyping platforms and FPGAs to validate designs before moving to silicon
Requirements:
  • Bachelors in Electrical/Computer Engineering with 15 years of relevant industry experience, or Masters in Electrical/Computer Engineering with 13 years or PhD in Electrical/Computer Engineering with 8 years preferred
  • 10+ years of experience in ASIC design with hands-on expertise in both frontend (RTL) and backend design processes
  • Experience in ASIC physical design flows, including synthesis, place and route, clock tree synthesis, and timing closure
  • Experience in CPU/GPU/DSP RTL design, including knowledge of instruction sets (ARM, RISC-V, x86), out-of-order pipeline design, and performance tuning
  • Proficiency in tools such as Synopsys (Design Compiler, IC Compiler), Cadence, or Mentor Graphics
  • In-depth knowledge of Static Timing Analysis (STA), timing closure, and power optimization techniques
  • Experience with prototyping platforms (such as Zebu or FPGAs), including experience with FPGA-based validation and design iteration, will be a plus
What We Offer:

We offer a comprehensive package of benefits centered around the wellbeing of our employees and their loved ones. In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves. An investment in your future is an investment in ours.

We are an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status.

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