ASIC Design Verification Engineer

2 weeks ago


San Jose, California, United States Cisco Full time
About the Role

We are seeking a highly skilled ASIC STA Engineer to join our team at Cisco. As a key member of our Common Hardware Group, you will play a critical role in designing, developing, and testing complex ASICs for our core Switching, Routing, and Wireless products.

Key Responsibilities
  • Closing timing at block, sub-chip, and full-chip levels
  • Performing quality checks such as setup, hold, transition, and noise
  • Managing ECO tasks and developing methodologies for STA work
  • Collaborating with cross-functional teams to drive designs to closure
Requirements
  • Bachelor's degree in electrical or computer engineering (or equivalent field) with 7+ years of related work experience
  • Experience with integration for STA, including hyperscale and hierarchical analysis
  • Timing closure with various timing ECO, including transition, setup, hold, noise, xtalk, and power recovery
  • Familiarity with on-chip variation, including AOCV, POCV, and voltage, temperature, aging-based timing derates
  • Scripting skills in TCL, Perl, or Python
Preferred Qualifications
  • Master's degree in electrical or computer engineering (or equivalent field) with 5+ years of related work experience
  • Experience with synthesis tools, formal verification, and parasitic extraction
About Cisco

Cisco is a leader in the networking industry, and we're committed to innovation and digital transformation. We're an inclusive company that values diversity and equality, and we're passionate about making a difference in the world. If you're a talented and motivated individual who is looking for a challenging and rewarding role, we encourage you to apply.



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