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Senior ASIC Design Engineer

2 months ago

San Jose, California, United States Cadence Design Systems Full time
About the Role

Cadence Design Systems is seeking a highly skilled Senior ASIC Design Engineer to join our Palladium ASIC development team. As a key member of our team, you will be responsible for designing and developing complex ASICs for our industry-leading emulation platform.

Key Responsibilities
  • Design and develop complex ASICs for the Palladium emulation platform
  • Collaborate with cross-functional teams to integrate ASICs into the platform
  • Develop and maintain expertise in ASIC design flow and tools
  • Participate in the development of next-generation emulation processors
Requirements
  • Bachelor's in Computer Science or Electrical Engineering + 2 years of related experience; or Master's
  • Experience in RTL development of complex ASIC/SoC
  • Comfortable in Verilog and SystemVerilog for the development of complex logic systems
  • Aware of ASIC design flow and experience with design tools such as Incisive/NCSim, Genus/Design Compiler, STA with Tempus/PrimeTime, power analysis
  • Experience with Lint and CDC tool flows
  • Exposure to major IP and protocols, such as SERDES, PCIe and DDR4
What We Offer

Cadence Design Systems offers a competitive salary range of $131,600 to $244,400, as well as incentive compensation, benefits, and a comprehensive benefits package. We are an equal opportunity employer and welcome applications from diverse candidates.