Senior ASIC Design Engineer

5 hours ago


San Jose, California, United States Cadence Design Systems Full time
About the Role

Cadence Design Systems is seeking a highly skilled Principal Design Engineer to join our PHY Design team. As a core member of this team, you will play a critical role in the development of advanced semiconductor chips that enable our customers to create revolutionary products and experiences.

Key Responsibilities
  • Design and develop high-speed interfaces for ASICs and IPs
  • Collaborate with Physical Design teams to ensure timing closure and P&R
  • Participate in silicon bring-up with the validation team
  • Develop and maintain timing constraints for ASICs and IPs
  • Expertise in STA tools and flow, with a strong understanding of design methodologies
Requirements
  • BSEE or MSEE degree
  • At least 3-5 years of prior experience in timing and RTL design
  • Prior experience in collaborating with Physical Design teams in multiple successful ASIC/IP tapeouts
  • Strong command of synthesis, STA, design for test, and design methodologies
  • Ability to handle multiple projects/tasks successfully
Preferred Skills
  • Knowledge of DDR/GDDR DRAM protocol and high-speed PHYs
  • Proficiency in scripting languages (TCL and Perl)
  • Proficiency with synthesis, logic equivalence, DFT, and backend-related methodology and tools
About Cadence

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property to design advanced semiconductor chips. We are committed to creating a diverse environment and are proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.



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