Senior ASIC Design Engineer

7 hours ago


San Diego, California, United States InnoPhase IoT Full time
Senior ASIC Design Engineer

We are seeking a highly skilled Senior ASIC Design Engineer to join our team at InnoPhase IoT. As a key member of our design team, you will be responsible for the development of low-power WiFi and BT/BLE RTL designs and implementations.

Key Responsibilities:
  • Participate in high-level product specifications and contribute to the development of RTL designs.
  • Work closely with RTL design and verification engineers to ensure timely and efficient design implementation.
  • Run synthesis, STA setup, and logic equivalency checks to ensure design accuracy and efficiency.
  • Develop and refine scripting and analysis tools to automate and enhance ASIC development flow.
  • Collaborate with the physical design team to ensure seamless integration of RTL designs.
Requirements:
  • 4+ years of experience in RTL design using Verilog and SystemVerilog.
  • Experience in synthesis, timing closure for FPGA and/or ASICs.
  • Experience with front-end design and integration tasks including lint, CDC, synthesis, and developing timing ECOs.
  • BSEE or MSEE with experience in ASIC development and/or FPGA prototyping.
  • Ability to work independently and proactively identify and resolve issues.
Preferred Qualifications:
  • Experience in low-power design development involving multiple power and voltage domains.
  • Expertise in working with APB/AHB/AXI bus protocols.
  • Understanding of wireless standards, such as IEEE 802.11 and 802.15.

We offer a dynamic and innovative work environment where you can grow and develop your skills. If you are passionate about wireless IoT solutions and have a strong background in RTL design and verification, we encourage you to apply for this exciting opportunity.



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