Senior ASIC Design Engineer

2 days ago


San Diego, California, United States InnoPhase IoT Full time
About InnoPhase IoT

InnoPhase IoT is a cutting-edge technology company that brings together the best in innovation to create revolutionary ULP wireless IoT solutions and user experiences in home, building, and industrial automation, and wearables.

Job Description:

We are seeking a highly skilled Senior ASIC Design Engineer to contribute to the development of Low-Power WiFi, BT/BLE RTL design, and implementation. As a key member of our team, you will be involved in the design and development cycle, participating in high-level product specifications, RTL development, and working closely with RTL design and verification engineers.

Responsibilities:
  • Run synthesis, STA setup, and logic equivalency checks.
  • Run Linting, Clock-domain-crossing, Reset-domain-crossing checks.
  • Help run scripts to generate memories, memBIST, and DFT logic.
  • Contribute to micro-architecture, and develop SystemVerilog RTL with established guidelines to meet size, timing, and power target.
  • Develop, and refine scripting and analysis tools to automate and enhance ASIC development flow.
  • Work closely with RTL, and Physical Design teams at various stages of product development.
Requirements:
  • Eagerness to learn, collaborate, and enjoy debugging and problem-solving in a team environment.
  • Experience with Python, Perl, Tcl, and shell scripts.
  • 4+ years of experience in RTL design using Verilog, SystemVerilog.
  • Experience in synthesis, timing closure for FPGA and/or ASICs.
  • Experience with front-end design and integration tasks including lint, CDC, synthesis, and developing timing ECOs.
  • BSEE or MSEE, with experience in ASIC development and/or FPGA prototyping.
  • Ability to work independently, and proactively identify and resolve issues.
  • Experience with Incisive/Excellium/VCS, Verdi, Jasper/Spyglass or equivalent tools.
Preferred Qualifications:
  • Experience in Low Power design development (UPF/CPF), involving multiple power, and voltage domains.
  • Expertise in working w/ APB/AHB/AXI bus protocols.
  • Understanding of wireless standards, such as IEEE 802.11, 802.15, Bluetooth is a plus, but not required.
  • Experience with lab debug, multi-team, multi-site working environment is a strong plus.
  • Experience using PowerArtist/Joules and providing actionable feedback into design.


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