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Experienced RTL Microarchitecture Specialist

2 months ago

California, United States DAC Search Inc Full time

Company Overview: DAC Search Inc/Richard Goldstein is dedicated to providing specialized recruiting services for the Semiconductor, EDA, and AI Chip sectors, with a focus on innovative startups.

About the Client: Our client is at the forefront of developing foundational technologies for chiplet-based semiconductor design. As an early-stage startup, they are pioneering advancements in the multi-chiplet system-on-package paradigm. Their mission is to drive the next wave of growth in the semiconductor industry, and they are seeking passionate professionals to join their experienced and dynamic team. The founding members have a proven track record, having successfully led a previous startup that was acquired by a major chip company, earning significant credibility within the industry. The executive team and board are exceptionally strong.

Position Overview: We are looking for a seasoned RTL Microarchitect who thrives in startup environments and is excited about the challenges they present.

Location: This role requires on-site presence in either Santa Clara, CA or Bengaluru, India. The small team values daily collaboration and cohesiveness.

Key Responsibilities:

  • Design and develop microarchitectures for a range of highly configurable IPs.
  • Ensure optimal performance, power efficiency, and area through microarchitecture and RTL coding.
  • Collaborate with software teams to define configuration requirements and verification collateral.
  • Engage with verification teams on assertions, test plans, debugging, and coverage.

Qualifications and Preferred Skills:

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Computer Science.
  • 8+ years of hands-on experience in microarchitecture and RTL development.
  • Proficient in Verilog and System Verilog.
  • Familiarity with industry-standard EDA tools and methodologies.
  • Experience with large, high-speed, pipelined, stateful designs, and low-power designs.
  • In-depth knowledge of on-chip interconnects and NoCs.
  • Experience with ARM ACE/CHI or similar coherency protocols.
  • Experience designing IP blocks for caches, cache coherency, memory subsystems, interconnects, and NoCs.
  • Familiarity with RAS designs, QoS in fabrics, and PCIe/IO is advantageous.
  • Experience with modern programming languages such as Python is a plus.
  • Excellent problem-solving abilities and attention to detail.
  • Strong communication and collaboration skills.

We encourage interested candidates to apply directly through our website.