Current jobs related to Senior IP Design Verification Engineer - San Jose - Intel

  • Senior Applications Engineer – DDR Design IP

    1 month ago

    San Jose, California, United States Cadence Design Systems Full time

    Unlock Your Potential as a Senior Applications EngineerCadence Design Systems is seeking a highly skilled Senior Applications Engineer to join our team. As a key member of our Memory IP team, you will play a critical role in developing and delivering industry-leading DDR Design IP solutions.As a Senior Applications Engineer, you will be responsible for...

  • IP Design Verification Engineer

    4 weeks ago

    San Jose, California, United States Intel Full time

    Job Details:Job Description: Intel is seeking a skilled logic validation engineer to join the Foundational Security team (FST) and contribute to the development of scalable IP designs.The ideal candidate will be responsible for validating new IP roadmap features, ensuring the quality of design, and developing test-plans, verification environment, and driving...

  • Senior Principal Design Engineer

    1 month ago

    San Jose, California, United States Cadence Design Systems Full time

    Job Title: Senior Principal Design EngineerCadence Design Systems is seeking an experienced Senior Principal Design Engineer to join our Compute Systems Group (CSG). As a key member of our team, you will be responsible for integrating and supporting Cadence IP products in system reference designs.Responsibilities:Integrate and validate reference designs...

  • Senior Principal Design Engineer

    2 weeks ago

    San Jose, California, United States Cadence Design Systems Full time

    Job Title: Senior Principal Design EngineerCadence Design Systems is seeking an experienced Senior Principal Design Engineer to join our team. As a key member of our Compute Systems Group (CSG), you will play a critical role in developing and licensing IP designs for SoC and ASIC systems.Job Summary:The CSG Central Applications Engineering team is looking...

  • Senior Principal Design Engineer

    2 weeks ago

    San Jose, California, United States Cadence Design Systems Full time

    Job Title: Senior Principal Design EngineerCadence Design Systems is seeking a highly experienced Senior Principal Design Engineer to join our Compute Systems Group (CSG). As a key member of our team, you will be responsible for integrating and supporting Cadence IP products in system reference designs.Key Responsibilities:Integrate and validate reference...

  • Senior ASIC Design Verification Engineer

    4 weeks ago

    San Jose, California, United States Mirafra Technologies Full time

    Design Verification/ Responsibilities:We are seeking a highly skilled Senior ASIC Design Verification Engineer to join our team at Mirafra Technologies.Develop and implement verification methodologies and testbenches for digital and mixed-signal blocks.Test plan, coverage analysis, and closure for parallel link and SerDes IP blocks and on-chip...

  • Senior Principal Design Engineer

    2 weeks ago

    San Jose, California, United States Cadence Design Systems Full time

    Job Description:Cadence Design Systems is seeking an experienced Senior Principal Design Engineer to join our Compute Systems Group (CSG) Central Applications Engineering team. As a key member of this team, you will be responsible for integrating and supporting Cadence IP products in system reference designs.The ideal candidate will have extensive knowledge...

  • FPGA Soft IP Design Verification Lead Engineer

    4 weeks ago

    San Jose, California, United States Intel Full time

    Job DescriptionAs a Lead Verification Engineer for FPGA IPs at Intel, you will be responsible for carrying out design validation for Intel's next-generation IP's across the Intel FPGA IP product portfolios. The charter of the IP verification and validation team is to verify and validate the IP for robust functionality from functional simulation and FPGA...

  • FPGA Soft IP Design Verification Lead Engineer

    2 weeks ago

    San Jose, California, United States Intel Full time

    Job Title: FPGA Soft IP Design Verification Lead Engineer Job Summary: We are seeking a highly skilled FPGA Soft IP Design Verification Lead Engineer to join our team at Intel. As a key member of our Programmable Solutions Group, you will be responsible for leading the design verification and validation of our next-generation FPGA IPs. Your expertise in...

  • FPGA Soft IP Design Verification Lead Engineer

    4 weeks ago

    San Jose, California, United States Intel Full time

    Job DescriptionIn the context of Intel's Programmable Solutions Group (PSG), this position plays a crucial role in the development of high-speed protocol IP portfolios. As a Lead Engineer for FPGA Soft IP Design Verification, you will be responsible for carrying out design validation for Intel's next-generation IP's across the FPGA IP product portfolios.Key...

  • FPGA Soft IP Design Verification Lead Engineer

    3 weeks ago

    San Jose, California, United States Intel Full time

    Job DescriptionIn the Programmable Solutions Group (PSG) at Intel, we are seeking a highly skilled FPGA Soft IP Design Verification Lead Engineer to join our team. As a key member of our IPSE group, you will be responsible for carrying out design validation for Intel's next-generation IP's across the Intel FPGA IP product portfolios.The successful candidate...

  • Senior Principal Design Engineer

    2 weeks ago

    San Jose, California, United States Cadence Design Systems Full time

    Cadence Design Systems is seeking a highly experienced Senior Principal Design Engineer to join our Compute Systems Group (CSG).The CSG develops and licenses IP designs for SoC and ASIC systems, including high-performance DSPs, CPUs, Interface IP, DDR controllers, hardware accelerators, and subsystems.This role will involve integrating and supporting Cadence...

  • Senior ASIC Design Verification Engineer

    1 week ago

    San Jose, California, United States Chelsea Search Group Full time

    Job Summary:Chelsea Search Group is seeking a highly skilled Senior ASIC Design Verification Engineer to join our team. As a key member of our design verification team, you will be responsible for developing and implementing test benches, test plans, and test cases using SystemVerilog and UVM. Your expertise in developing SV functional coverage models and...

  • FPGA Soft IP Design Verification Lead Engineer

    4 weeks ago

    San Jose, California, United States Intel Full time

    Job DescriptionIn the rapidly evolving landscape of semiconductor technology, Intel's Programmable Solutions Group (PSG) is poised to revolutionize the industry with its cutting-edge FPGA solutions. As a key player in this endeavor, we are seeking a highly skilled FPGA Soft IP Design Verification Lead Engineer to join our team.This position is a critical...

  • Senior ASIC Design Verification Engineer

    2 weeks ago

    San Jose, California, United States Mirafra Technologies Full time

    Design Verification/ Responsibilities:Develop and implement verification methodologies and testbenches for digital and mixed-signal blocks to ensure high-quality and reliable designs.Collaborate with cross-functional teams to create comprehensive test plans, conduct coverage analysis, and drive closure for parallel link and SerDes IP blocks and on-chip...

  • Senior ASIC Verification Engineer

    2 weeks ago

    San Jose, California, United States European Tech Recruit Full time

    Senior ASIC Verification Engineer - AI and Data CenterWe are partnering with a leading Semiconductor organization to accelerate AI computing in data centers and HPC. As a Senior ASIC Verification Engineer, you will play a critical role in ensuring the pre-silicon correctness and quality of a multi-million gate ASIC that integrates computational accelerators...

  • FPGA Soft IP Design Verification Lead Engineer

    2 weeks ago

    San Jose, California, United States Intel Full time

    Job DescriptionIn 2023, Intel announced a significant change in its business strategy, separating Altera as a standalone business unit, effective January 1, 2024. This position is part of that strategy and will transition to a standalone company in the future.Key Responsibilities:Create comprehensive verification and validation plans based on IP/FPGA...

  • Senior UVM Design Verification Engineer

    1 month ago

    San Jose, California, United States Advanced Micro Devices , Inc. Full time

    About the RoleWe are seeking a skilled Design Verification Engineer to join our team at Advanced Micro Devices, Inc. This is an exciting opportunity to work on cutting-edge technologies and contribute to the development of industry-leading products.Key ResponsibilitiesDevelop and maintain tests for functional verification and performance verification at the...

  • Senior ASIC Verification Engineer

    3 days ago

    San Jose, California, United States USA Tech Recruit Full time

    Job Title: Senior ASIC Verification EngineerJob Summary: We are seeking a highly skilled Senior ASIC Verification Engineer to join our team at USA Tech Recruit. As a Senior ASIC Verification Engineer, you will be responsible for ensuring the pre-silicon correctness and quality of a multi-million gate ASIC that integrates computational accelerators and...

  • Senior Verification Engineer

    3 weeks ago

    San Jose, California, United States Advanced Micro Devices , Inc. Full time

    Job Title: SOC / IP Design Verification EngineerWe are seeking a highly skilled SOC / IP Design Verification Engineer to join our team at Advanced Micro Devices, Inc. (AMD). As a key member of our Verification Engineering team, you will play a critical role in ensuring the quality and reliability of our cutting-edge SOC and IP designs.About the Role:This is...

Senior IP Design Verification Engineer

3 months ago

San Jose, United States Intel Full time

Job Details:

Job Description:

The Foundational Security team (FST) is looking for logic validation engineers keen to work on a scalable IP design. The candidate will be responsible for the validation of new IP roadmap features as part of FST's HW IP developing HW security for various market segments across Intel. As a member of the team, the candidate would be responsible for driving scalable IP development while also making the Design Integration and SOC delivery a fully automated solution. The candidate will be part of an IP team working closely with other verification engineers, RTL design engineers, micro-architects, architects, and other team members in determining the proper implementation strategy for new design, ensuring quality of design, and developing test-plans, verification environment, and driving delivery to SoC. They will have an opportunity to learn and contribute towards making Intel Hardware more secure. Behavioral traits:

Strong analysis, debugging skills, and creative in problem solving. Excellent communication and organization skills are critical, along with teamwork, and must demonstrate strong technical skills, along with having passion for design or validation. Must have strong orientation for Quality and Commit and Deliver and Drive Innovation/efficiencies and have strong strategic thinking to come up with paradigm shift solutions to critical design/validation challenges. Leadership. Qualifications:

Minimum Qualifications: The candidate must possess a minimum of a bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent with 5 years of experience or a Master's degree in Microelectronics along with 3+ years of relevant experience. Experience to be considered but not limited to: System Verilog OVM / UVM Capable in developing test plans, tests, and verification environment based on High Level Architecture specifications. Testbench development Coverage-based random constraint simulation Object-Oriented Programming (OOP) Advanced English level Costa Rican unrestricted work permit Desirable Qualifications: Scripting (Python/Perl/Shell) RTL simulators RTL model build Interactive debugger Power-aware simulation Power management, IOSF, AHB, PCI express or any industry standard BUS protocol Job Type:

Experienced Hire Shift:

Shift 1 (Costa Rica) Primary Location:

Costa Rica, San Jose Additional Locations:

Business group:

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations. DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost-efficient and effective manner. Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust

N/A Work Model for this Role: This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances, the work model may change to accommodate business needs.

#J-18808-Ljbffr