FPGA Soft IP Design Verification Lead Engineer

3 days ago

San Jose, California, United States Intel Full time
Job Description

As a Lead Verification Engineer for FPGA IPs at Intel, you will be responsible for carrying out design validation for Intel's next-generation IP's across the Intel FPGA IP product portfolios. The charter of the IP verification and validation team is to verify and validate the IP for robust functionality from functional simulation and FPGA development kit-based HW validation.

Key Responsibilities:
  • Create comprehensive verification and validation plans based on IP/FPGA architecture specifications and carry out all the IP validation tasks.
  • Develop IP/subsystem/system-level testbenches, create tests, and necessary coverage goals based on specification to verify the implementation.
  • Review verification and validation results against the coverage goals. Write, analyze, and achieve coverage metrics.
  • Work with cross-functional teams and prepare/support IP functional validation tests for IP bring-up on actual FPGA development kits, maximizing FPGA hardware capability to bring substantial improvement to IP quality and usability for Altera FPGA IP product portfolios.
  • Integrate Synopsys VIP and their usage to aid end-to-end testing Ethernet/MACSEC/IPSEC protocol testing.
  • Develop verification and validation tools and flows, as needed.
  • Apply advanced techniques to achieve verification and validation with the highest quality, productivity, and time-to-market.
  • Excellent communication skills.
Qualifications:
  • BS/MS in Electrical Engineering, Computer Engineering, or a closely related field of study plus 8 years of industry experience.
  • 8+ years of experience developing verification collateral in Verilog, System Verilog, and UVM.
  • 7 years with Ethernet protocol verification is required.
  • Fluency in UVM, must have 7 years prior work experience with complex coverage-driven random constraint UVM environments.
  • Should have expertise in network security protocols: Ethernet/MACSEC/IPSEC end-to-end testing. Prefer candidates to be well-versed in PCIe and Memory security solutions.
  • 7 years of experience creating test plans from high-level specifications and developing test cases.
  • 7 years of experience of debugging skills to narrow down and isolate issues between RTL design and testbench or test case is required.
  • 4+ years of leading complex projects and leadership experience working with cross-functional teams.

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