Senior ASIC Design Verification Engineer
2 days ago
We are seeking a highly skilled Senior ASIC Design Verification Engineer to join our team at Mirafra Technologies.
- Develop and implement verification methodologies and testbenches for digital and mixed-signal blocks.
- Test plan, coverage analysis, and closure for parallel link and SerDes IP blocks and on-chip interconnects.
To be successful in this role, you will need:
- A Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
- At least 10 years of experience in ASIC design verification, with a strong background in System Verilog and UVM testbench development.
- Experience working with version control software, such as Git.
- Proficiency in scripting or programming languages.
We are looking for candidates with:
- Experience working on digital designs with multiple clock domains and clock dividers.
- Experience in verification of SerDes IP block interfaces in a complex SoC fabric environment.
- Experience in verification of the PCS, PMA SerDes layers and internal SerDes digital backends.
- Experience with verification of HBM memory interfaces (PHY and controller).
- Experience in formal model equivalence checking tools and verification methodology.
We also require:
- Proficiency in Python programming language.
Mirafra Technologies is an equal opportunities employer and welcomes applications from all qualified candidates.
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