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FPGA Soft IP Design Verification Lead Engineer

1 month ago


San Jose, California, United States Intel Full time
Job Description

In 2023, Intel announced a significant change in its business strategy, separating Altera as a standalone business unit, effective January 1, 2024. This position is part of that strategy and will transition to a standalone company in the future.

Key Responsibilities:
  • Create comprehensive verification and validation plans based on IP/FPGA architecture specifications and execute all IP validation tasks.
  • Develop IP/subsystem/system level testbenches, create tests, and set coverage goals based on specifications to verify implementation.
  • Review verification and validation results against coverage goals, write, analyze, and achieve coverage metrics.
  • Collaborate with cross-functional teams and prepare/support IP functional validation tests for IP bring-up on actual FPGA development kits, maximizing FPGA hardware capability to improve IP quality and usability for Altera FPGA IP product portfolios.
  • Integrate Synopsys VIP and utilize it for end-to-end testing of Ethernet/MACSEC/IPSEC protocols.
  • Develop verification and validation tools and flows as needed.
  • Apply advanced techniques to achieve verification and validation with high quality, productivity, and time-to-market.
  • Excellent communication skills.
Qualifications:
  • BS/MS in Electrical Engineering, Computer Engineering, or a closely related field of study, plus 8 years of industry experience.
  • 8+ years of experience developing verification collateral in Verilog, System Verilog, and UVM.
  • 7 years of experience with Ethernet protocol verification.
  • Fluency in UVM, with 7 years of prior work experience in complex coverage-driven random constraint UVM environments.
  • Expertise in network security protocols: Ethernet/MACSEC/IPSEC end-to-end testing. Prefer candidates well-versed in PCIe and Memory security solutions.
  • 7 years of experience creating test plans from high-level specifications and developing test cases.
  • 7 years of experience in debugging skills to narrow down and isolate issues between RTL design and testbench or test case.
  • 4+ years of leading complex projects and leadership experience working with cross-functional teams.
Preferred Qualifications:
  • Must have created complex UVM environments from scratch.
  • FPGA experience is a plus.
Inside this Business Group:

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today.

Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency.

PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation.

We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees.

That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.