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Senior Applications Engineer – DDR Design IP

2 months ago

San Jose, California, United States Cadence Design Systems Full time
Unlock Your Potential as a Senior Applications Engineer

Cadence Design Systems is seeking a highly skilled Senior Applications Engineer to join our team. As a key member of our Memory IP team, you will play a critical role in developing and delivering industry-leading DDR Design IP solutions.

As a Senior Applications Engineer, you will be responsible for generating technical collateral, running simulations and synthesis, and presenting IP demos to customers. You will work closely with our IP Sales staff, marketing, and R&D teams to win opportunities and drive business growth.

We are looking for a talented individual with a strong background in computer architecture, electronics circuits, and Verilog HDL. You should have experience with simulation and synthesis tools, as well as excellent presentation skills and verbal/written communication skills.

Responsibilities:
  1. Generate technical collateral for Memory IP solutions
  2. Run simulations and synthesis to enable IP benchmarking and analysis
  3. Present IP demos to customers and stakeholders
  4. Collaborate with IP Sales staff, marketing, and R&D teams to win opportunities and drive business growth
  5. Stay up-to-date with industry trends and developments in DDR Design IP
Qualifications:
  1. BS/MS in EE, CE, or related majors
  2. Strong background in computer architecture and electronics circuits
  3. Experience with Verilog HDL and simulation/synthesis tools
  4. Excellent presentation skills and verbal/written communication skills
Nice to Have:
  1. Familiarity with one or more DRAM protocols – DDR4/5, LPDDR4/5/5X, HBM2/3, GDDR6
  2. Perl/Python scripting experience
  3. Experience with memory subsystem verification and/or performance analysis
  4. Strong knowledge of ASIC flow, RTL design in Verilog, System Verilog, and FPGA design
  5. Knowledge of AXI, DFI protocols
  6. Working knowledge of memory controller and memory PHY

Cadence Design Systems offers a competitive salary range of $120,400 to $223,600, as well as incentive compensation, benefits, and opportunities for growth and development. We are an equal opportunity employer and welcome applications from diverse candidates.