FPGA Soft IP Design Verification Lead Engineer
1 week ago
In the Programmable Solutions Group (PSG) at Intel, we are seeking a highly skilled FPGA Soft IP Design Verification Lead Engineer to join our team. As a key member of our IPSE group, you will be responsible for carrying out design validation for Intel's next-generation IP's across the Intel FPGA IP product portfolios.
The successful candidate will have a strong background in verification and validation of high-speed protocol IPs, with expertise in UVM, Verilog, and System Verilog. They will be responsible for creating comprehensive verification and validation plans, developing testbenches, and writing directed and random test cases. The ideal candidate will also have experience with Synopsys VIP and its usage for end-to-end testing of Ethernet/MACSEC/IPSEC protocols.
We are looking for a highly motivated and experienced engineer who can work effectively in a cross-functional team environment. The successful candidate will have excellent communication skills and be able to collaborate with other teams to prepare and support IP functional validation tests for IP bring-up on actual FPGA development kits.
Key Responsibilities- Create comprehensive verification and validation plans based on IP/FPGA architecture specifications
- Develop testbenches, create tests, and necessary coverage goals based on specification
- Review verification and validation results against coverage goals
- Work with cross-functional teams to prepare and support IP functional validation tests
- Integrate Synopsys VIP and its usage for end-to-end testing of Ethernet/MACSEC/IPSEC protocols
- Develop verification and validation tools and flows as needed
- BS/MS in Electrical Engineering, Computer Engineering, or a closely related field of study plus 8 years of industry experience
- 8+ years of experience developing verification collateral in Verilog, System Verilog, and UVM
- 7 years of experience with Ethernet protocol verification
- Fluency in UVM and 7 years of prior work experience with complex coverage-driven random constraint UVM environments
- Expertise in network security protocols: Ethernet/MACSEC/IPSEC end-to-end testing
- 7 years of experience creating test plans from high-level specifications and developing test cases
- 7 years of experience in debugging skills to narrow down and isolate issues between RTL design and testbench or test case
- 4+ years of leading complex projects and leadership experience working with cross-functional teams
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as benefit programs which include health, retirement, and vacation.
Find more information about all of our amazing benefits here:
Annual Salary Range for jobs which could be performed in the US:
$144,501.00-$217,311.00
Salary range dependent on a number of factors including location and experience.
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San Jose, California, United States Intel Full timeJob Title: FPGA Soft IP Design Verification Lead Engineer Job Summary: We are seeking a highly skilled FPGA Soft IP Design Verification Lead Engineer to join our team at Intel. As a key member of our Programmable Solutions Group, you will be responsible for leading the design verification and validation of our next-generation FPGA IPs. Your expertise in...
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