ASIC Engineer, Design Verification_
3 days ago
**Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications.As a Design Verification Engineer, you will be part of a dynamic team working with the best in the industry, focused on developing innovative ASIC solutions for Meta’s data center applications. You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure. Along with traditional simulation, you will be able to use other approaches like Formal and Emulation to achieve a bug-free design. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer, Design Verification Responsibilities: 1. Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification. 2. Develop functional tests based on verification test plan. 3. Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage. 4. Debug, root-cause and resolve functional failures in the design, partnering with the Design team. 5. Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality. 6. Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry. **Minimum Qualifications:** Minimum Qualifications: 7. Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. 8. 5+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification. 9. Track record of 'first-pass success' in ASIC development cycles. 10. 5+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies. 11. Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments. 12. Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle. **Preferred Qualifications:** Preferred Qualifications: 13. Experience in development of UVM based verification environments from scratch. 14. Experience verifying GPU/CPU designs. 15. Experience with micro-architectural performance verification. 16. Experience with Design verification of Data-center applications like Video, AI/ML and Networking designs. 17. Experience with verification of ARM/RISC-V based sub-systems or SoCs. 18. Experience with IP or integration verification of high-speed interfaces like PCIe, RoCE, DDR, HBM, Ethernet. 19. Experience in one or more of the following areas along with functional verification - SV Assertions, Formal, Emulation. 20. Experience working across and building relationships with cross-functional design, model and emulation teams. 21. Experience with revision control systems like Mercurial(Hg), Git or SVN. **Public Compensation:** $136,000/year to $203,000/year + bonus + equity + benefits **Industry:** Internet **Equal Opportunity:** Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment. Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@fb.com.
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ASIC Engineer, Design Verification
5 days ago
Sunnyvale, United States Meta Full timeASIC Engineer, Design Verification Sunnyvale, CA | Austin, TX | Menlo Park, CAMeta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications. As a Design Verification Engineer, you will be part of...
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ASIC Engineer, Design Verification
5 days ago
Sunnyvale, California, United States Meta Full timeASIC Engineer, Design VerificationSunnyvale, CA | Austin, TX | Menlo Park, CAMeta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications.As a Design Verification Engineer, you will be part of a...
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ASIC Engineer, Design
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Sunnyvale, California, United States Facebook Full timeMeta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs in fields such as machine learning, video transcoding and network acceleration. We are looking for talented individuals with deep experience that span one or more of the key areas required to build successful world-class complex SoC and IP for data center...
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ASIC Engineer, Design
4 weeks ago
Sunnyvale, United States Facebook Full timeMeta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs in fields such as machine learning, video transcoding and network acceleration. We are looking for talented individuals with deep experience that span one or more of the key areas required to build successful world-class complex SoC and IP for data center...
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RTL ASIC Design Engineer
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Sunnyvale, United States Wipro Full timeRTL ASIC Design Engineers with 8 to 15+ years of experience.No of Openings: 2 Sunnyvale, CAJob Description:· 8+ years of Exp with Logic design /micro-architecture / RTL coding is a must.· Expertise in Verilog & System Verilog is a must.· Experience in Synthesis / Understanding of timing concepts for ASIC is required.· Experience in design of DDR / USB...
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Sunnyvale, United States Maxonic Full timeMaxonic maintains a close and long-term relationship with our direct client. In support of their needs, we are looking for a ASIC EngineerJob Description:Job Title: ASIC Engineer As a Design Verification Engineer, you will be part of a dynamic team working with the best in the industry, focused on developing innovative ASIC solutions for Facebook's data...
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ASIC Engineer, Design Verification
4 weeks ago
Sunnyvale, United States META Full timeSummary: Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications.As a Design Verification Engineer, you will be part of a dynamic team working with the best in the industry, focused on...
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ASIC Engineer, Design Verification
4 weeks ago
Sunnyvale, United States Meta Inc Full timeSummary: Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications.As a Design Verification Engineer, you will be part of a dynamic team working with the best in the industry, focused on...
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ASIC Engineering Manager, Design Verification
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Sunnyvale, California, United States Meta Inc Full timeSummary:The ideal candidate will be a consensus-driven leader with management and leadership experience in small to large size organizations, with comprehensive system and silicon development experience, and a proven track record of first-pass success in ASIC and Systems.Required Skills:ASIC Engineering Manager, Design Verification Responsibilities:Manage an...
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ASIC Engineer, Design Verification
2 weeks ago
Sunnyvale, California, United States META Full timeMeta is hiring ASIC Design Verification Engineer within the Infrastructure organization.We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications.As a Design Verification Engineer, you will be part of a dynamic team working with the best in the industry, focused on developing...
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Sunnyvale, United States Wipro Full time8+years of hands-on Verilog programming experience for ASIC, with proficiency in front-end Cadence tools and methodologies, along with a demonstrable track record of delivering complex RTL logic designs for multi-million gate high speed processors/ASICs. Knowledge of high speed compute (e.g. floating point vector processing units (VPU), GPU shader hardware...
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Senior ASIC Design Engineer
2 weeks ago
Sunnyvale, United States Wipro Full time8+years of hands-on Verilog programming experience for ASIC, with proficiency in front-end Cadence tools and methodologies, along with a demonstrable track record of delivering complex RTL logic designs for multi-million gate high speed processors/ASICs. Knowledge of high speed compute (e.g. floating point vector processing units (VPU), GPU shader hardware...
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Senior ASIC Design Engineer
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Sunnyvale, United States Wipro Full time8+years of hands-on Verilog programming experience for ASIC, with proficiency in front-end Cadence tools and methodologies, along with a demonstrable track record of delivering complex RTL logic designs for multi-million gate high speed processors/ASICs. Knowledge of high speed compute (e.g. floating point vector processing units (VPU), GPU shader hardware...
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Senior ASIC Design Engineer
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Sunnyvale, United States Wipro Full time8+years of hands-on Verilog programming experience for ASIC, with proficiency in front-end Cadence tools and methodologies, along with a demonstrable track record of delivering complex RTL logic designs for multi-million gate high speed processors/ASICs. Knowledge of high speed compute (e.g. floating point vector processing units (VPU), GPU shader hardware...
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Senior ASIC Design Engineer
2 weeks ago
Sunnyvale, United States Wipro Full time8+years of hands-on Verilog programming experience for ASIC, with proficiency in front-end Cadence tools and methodologies, along with a demonstrable track record of delivering complex RTL logic designs for multi-million gate high speed processors/ASICs. Knowledge of high speed compute (e.g. floating point vector processing units (VPU), GPU shader hardware...
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ASIC/RTL/SOC Design Engineer
2 weeks ago
Sunnyvale, United States Wipro Full timeJob Title: ASIC/RTL/SOC Design EngineerDuration: Full TimeLocation: Sunnyvale, CA Description :Logic design /micro-architecture / RTL coding is a must.Expertise in Verilog & System Verilog is a must.Experience in Synthesis / Understanding of timing concepts for ASIC is required.Static checking tools like Lint, CDC, RDC, Spyglass DFT etc experience...
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ASIC Engineer
2 weeks ago
Sunnyvale, United States Juniper Networks Full timeENGINEERING- Juniper Networks in Sunnyvale, CA seeks ASIC Engineer: Define, architect, code, and deliver complex digital designs and verification suites/tests for ASICs. Develop block level verification environment using Universal Verification Methodology (UVM) and System Verilog. Part-time telecommuting allowed. $184,000/yr. - $211,200/yr. Email res (must...
