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ASIC/RTL/SOC Design Engineer

7 months ago

Sunnyvale, United States Wipro Full time

Job Title: ASIC/RTL/SOC Design Engineer

Duration: Full Time

Location: Sunnyvale, CA

Description :

  • Logic design /micro-architecture / RTL coding is a must.
  • Expertise in Verilog & System Verilog is a must.
  • Experience in Synthesis / Understanding of timing concepts for ASIC is required.
  • Static checking tools like Lint, CDC, RDC, Spyglass DFT etc experience required.
  • Experience in design of DDR / USB /SATA/ PCIe controller or such complex protocols is a plus.
  • Hands on experience in Multi Clock designs, Asynchronous interface is a must.
  • Knowledge of low power concepts and experience is a plus.