Senior RTL ASIC Design Engineer

1 week ago


Sunnyvale, United States ManpowerGroup Full time

Work location : Sunnyavale CA/ Austin TX


Note: We are looking for RTL ASIC front end designers only, not FPGA Design


Keywords: RTL ASIC design, SOC design, IP design, Lint, CDC, RTL Architecture design


Experience : 8 - 15 Years

JD:

  • Architecture and microarchitecture of System on a Chip (“SOC”) subsystems, Intellectual Property Functional Blocks (“IPs”), sub-IPs, modules, and library components
  • Digital design, using System Verilog and/or Verilog RTL, RTL generators (in Python), and/or high-level synthesis (“HLS”). RTL integration of SoC subsystems, IPs, sub-IPs, modules, and library components
  • SoC-level integration
  • Support mapping of RTL on Zebu and HAPS for IP bring up and E2E validation
  • Design for low power and power intent design using Unified Power Format (“UPF”)
  • Constraint development, synthesis, timing closure, and optimization of the design
  • Code quality checks, including but not limited to Linting, Clock Domain Crossing, Reset Domain Crossing
  • Debug and bug fixes
  • Exp in Lint, CDC, spyglass tool is preferred.


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