Senior Principal ASIC Design Engineer
4 weeks ago
As a key member of Fortinet's ASIC design team, you will play a principal role in developing next-gen SOC architecture, performing IP integration, chip-level RTL design & verification, and leading low-power design methodology.
Candidate must be able to work with self-motivation and deliver on commitments with challenging schedules, lead design teams through various phases of ASIC design process including RTL design, chip-level verification, coverage analysis, synthesis, and STA.
Candidate must possess solid knowledge in SOC design techniques, analog IPs, high-speed IO protocols, CPF/UPF power design flow, and lint/CDC tools.
Job Responsibilities:- Lead architecture design to shape micro-architecture of next-generation SOC FortiASIC.
- Work with IP teams to review verification test plan, coverage analysis, and full-chip simulation.
- Design implementation using Verilog HDL and synthesis.
- Work with physical design teams to verify constraints, optimize place & route, and achieve timing closure.
- A self-starter with ability to manage time effectively and work within a diverse team environment.
- Experienced in design and implementation of complex multi-million gate SOCs.
- Familiarity with ARM subsystem, SMP multi-socket cache coherency.
- Familiarity with high-speed IP protocols such as PCIe5 and DDR5.
- Preferred experience in chiplet multi-die system-in-package design.
- Strong experience designing digital circuits using Verilog HDL.
- Strong experience in formal verification of digital design.
- Fluent in C, C++, assembly, and scripting languages.
- Excellent communication skills.
MS & BS in Electrical Engineering or related field with 10+ years of SOC ASIC design experience.
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