ASIC Design Engineer
3 weeks ago
Meta is seeking a highly skilled ASIC Design Engineer to join our Infrastructure organization. As a key member of our team, you will be responsible for designing and developing cutting-edge machine learning ASICs that deliver world-class inference and training performance.
Key Responsibilities:
- Develop micro-architecture and RTL designs using Verilog, System Verilog, and HLS.
- Optimize designs for power, area, and performance.
- Collaborate with verification and emulation teams to develop test plans and debug designs.
- Work with implementation teams to close designs on timing and power.
Requirements:
- 3+ years of silicon development experience.
- Experience with Verilog or System Verilog.
- Experience in micro-architecture and RTL development for complex control and data path IPs.
Preferred Qualifications:
- Experience in data path development.
- Experience with synthesis and timing closure.
Compensation:
$95,400/year to $166,000/year + bonus + equity + benefits
Industry: Internet
Equal Opportunity:
Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based on race, religion, color, national origin, sex, sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics.
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