Senior Principal ASIC Design Engineer
3 days ago
Fortinet is seeking a highly skilled Senior Principal ASIC Design Engineer to join our team. As a key member of our ASIC design team, you will play a principal role in developing next-gen SOC architecture, performing IP integration, chip-level RTL design & verification, and leading low-power design methodology.
Key Responsibilities:- Lead architecture design to shape micro-architecture of next-generation SOC FortiASIC.
- Work with IP teams to review verification test plan, coverage analysis, and full-chip simulation.
- Design implementation using Verilog HDL and synthesis.
- Work with physical design teams to verify constraints, optimize place & route, and achieve timing closure.
- Experienced in design and implementation of complex multi-million gate SOCs.
- Familiarity with ARM subsystem, SMP multi-socket cache coherency.
- Familiarity with high-speed IP protocols such as PCIe5 and DDR5.
- Preferred experience in chiplet multi-die system-in-package design.
- Strong experience designing digital circuits using Verilog HDL.
- Strong experience in formal verification of digital design.
- Fluent in C, C++, assembly, and scripting languages.
MS & BS in Electrical Engineering or related field with 10+ years of SOC ASIC design experience.
Fortinet offers a competitive salary range of $190,000-$260,000, as well as a comprehensive benefits package, including medical, dental, vision, life, and disability insurance, 401(k), 11 paid holidays, vacation time, and sick time. All roles are eligible to participate in the Fortinet equity program, and bonus eligibility is reviewed at time of hire and annually at the Company's discretion.
Fortinet is an equal opportunity employer and values diversity in our company. We encourage candidates from all backgrounds and identities to apply. We offer a supportive work environment and a competitive Total Rewards package to support you with your overall health and financial well-being.
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