RTL Lead
2 months ago
RTL Lead at Sunnyvale CA
RTL Lead
Location: Sunnyvale
Description:
- Experience in Logic design /micro-architecture / RTL coding is necessary.
- Experience in Verilog & System Verilog is necessary.
- Understanding of timing concepts for ASIC is required.
- Experience in design of DDR / USB /SATA/ PCIe controller or such complex protocols is a plus.
- Hands on experience in Multi Clock designs, Asynchronous interface is a must.
- Experience on tools utilized in all phases of ASIC development such as Lint, CDC, Simulation, chip architecture, RTL implementation, RTL synthesis, ASIC bring-up, and characterization.
- Knowledge of low power concepts and experience is a plus
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