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Senior ASIC Design Engineer

2 months ago


Sunnyvale, California, United States Amazon Services LLC Full time
About the Role

We are seeking a highly skilled Senior ASIC Design Engineer to join our Hardware Compute Group at Amazon Services LLC. As a key member of our team, you will be responsible for designing and developing hardware accelerator IP to be deployed in a range of Amazon devices.

Key Responsibilities
  • Design and Development: Microarchitect and design hardware accelerator IP in Verilog HDL, ensuring high-quality and efficient designs that meet the power, performance, and area goals for Amazon devices.
  • Methodology and Process: Help define and own ASIC design methodologies, ensuring seamless collaboration with cross-functional teams and stakeholders.
  • Leadership and Collaboration: Lead cross-functional SOC development activities, working closely with scientists, SoC Architects, software, and verification teams to develop IP that meets the required goals.
  • Technical Expertise: Provide technical leadership through personal example, mentorship, and strong teamwork, ensuring the delivery of high-quality IP to SoC product teams.
Requirements
  • Education: BS degree or higher in EE or CE or CS.
  • Experience: 5+ years or more of practical semiconductor ASIC design experience, including owning end-to-end design of major SOC blocks.
  • Skills: Successful tape-outs as an owner of a major design block, experience writing HDL in Verilog/SystemVerilog, understanding architectural models and algorithms in C/C++, proficient in design methodologies and EDA tools, experience working with Synthesis, timing, and design constraints.
Preferred Qualifications
  • Advanced Knowledge: In-depth knowledge of CPU, DSP, or programmable accelerators.
  • Experience: Experience working with RISC-V, SOC bringup and post-silicon validation, early power analysis, architecture/system engineering, developing with modern programming languages (Python, Java, C/C++), opensource technologies, and Linux.
  • Technical Expertise: Experience with gate-level testing and multi-clock design practices (CDC), working with software teams to tightly define the HW/SW interface, including control/status registers, and error handling.
  • Collaboration: Experience working closely with physical design teams to develop highly optimized ASICs with excellent power, performance, and area.
  • Microarchitecture: Experience in microarchitecture definition from architecture guidelines and model analysis.
  • RTL Coding and Debug: Experience in RTL coding and debug, as well as performance/power/area analysis and tradeoffs.
  • Timing Analysis: Experience in timing analysis and working with physical design teams to close timing.
  • Partner Collaboration: Experience in working with internal and external partners.