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Lead ASIC Digital Design Engineer

2 months ago

Sunnyvale, California, United States Synopsys Full time
Job Description

**About the Role**

Synopsys is seeking a highly skilled Senior ASIC Digital Design Engineer to join our Solution Group, DDRPHY IP team. As a key member of our team, you will be responsible for innovating and developing the latest world-class market-leading DesignWare DDRPHY IP solution.

Key Responsibilities:

  • Digital Microarchitecture Definition and Documentation: Develop and document digital microarchitectures for DDRPHY IP solutions.
  • RTL Logic Design, Debug, and Verification: Design, debug, and verify RTL logic for DDRPHY IP solutions, ensuring optimal timing, area, and power.

Requirements:

  • Education: Bachelor's or Master's degree in Electronics Engineering with at least 5 years of design experience.
  • Design Experience: Experience with synthesizable Verilog and System Verilog design concepts and implementation.
  • Front-end Design Flows: Experience with front-end design flows such as linting, synthesis, timing investigation and closure, cross-domain clocking, DFT, and power optimization techniques.
  • Communication Skills: Excellent communication skills and self-motivation.
  • DDR Memory and Architecture: Understanding of DDR memory and DDRPHY architecture is a plus.

What We Offer:

  • Competitive Salary: The base salary range for this role is between $122,000-$182,000.
  • Bonus and Equity: This role may be eligible for an annual bonus, equity, and other discretionary bonuses.
  • Total Rewards Package: Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package.

About Synopsys:

Synopsys is a leading provider of silicon IP products, including DDR IP solutions. Our team is passionate about innovating and developing cutting-edge technologies that enable our customers to create differentiated products.