Physical Design Engineer

Principal Application Engineer responsible for providing pre-sales and post-sales technical support for the Digital Implementation and Signoff tools. Will work closely with customers on bringing up flows at advanced nodes, and solving challenges in meeting power, performance and area (PPA) in vertical markets such as datacenter, ML/AI, networking and...

Technical/Functional Skills: BS/MS in Electrical Engineering or Computer Science 6+ year minimum of hands-on experience in ASIC design and design constraints level synthesis, place and route, timing closure. Standard PnR and signoff tools and their capabilities Understanding of basic power Analysis and power integrity Analysis Excellent English verbal...

Technical/FunctionalSkills: BS/MS in ElectricalEngineering or Computer Science 6+ year minimum ofhands-on experience in ASIC design and design constraints level synthesis, placeand route, timing closure. Standard PnR andsignoff tools and their capabilities Understanding of basicpower Analysis and power integrity Analysis Excellent Englishverbal and written...

Physical Design STA EngineerLocation:- San Jose, CA (Hybrid Schedule)Duration:- 6 MonthsPay rate:- $80 - $120/hr W2.Responsibilities of Physical Design STA EngineerPerform static timing analysis (STA) and timing optimization, generate and verifies timing constraints, performs SI/Noise analysis, and fixes timing & noise violations at full chip/block level for...

Job DescriptionJob DescriptionPhysical Design STA EngineerLocation:- San Jose, CA (Hybrid Schedule)Duration:- 6 MonthsPay rate:- $80 - $120/hr W2.Responsibilities of Physical Design STA EngineerPerform static timing analysis (STA) and timing optimization, generate and verifies timing constraints, performs SI/Noise analysis, and fixes timing & noise...

Physical Design STA EngineerLocation:- San Jose, CA (Hybrid Schedule)Duration:- 6 MonthsPay rate:- $80 - $120/hr W2.Responsibilities of Physical Design STA EngineerPerform static timing analysis (STA) and timing optimization, generate and verifies timing constraints, performs SI/Noise analysis, and fixes timing & noise violations at full chip/block level for...

Physical Design STA EngineerLocation:- San Jose, CA (Hybrid Schedule)Duration:- 6 MonthsPay rate:- $80 - $120/hr W2.Responsibilities of Physical Design STA EngineerPerform static timing analysis (STA) and timing optimization, generate and verifies timing constraints, performs SI/Noise analysis, and fixes timing & noise violations at full chip/block level for...

Job Title: Physical Design Engineer Duration: 12 mos. + potential extension(s) and/or conversion Location: San Jose, CA Description: •Perform physical implementation in Synopsys tools (ICC2) •Develop and maintain the tool flow to support the project. •Work with Team to enhance PD methodology. •Fixing DRC/LVS issues •Fixing voltage drop...

Job Title:Sr Physical Design Engineer Location: San Jose, CA POSITION SUMMARY 7-10+ Yrs of experience in doing hands on physical design for complete flow of Netlist to GDSII Preferred Tool experience on Client ICC2, DC, PT, Calibre OR Genus, Innovus, Tempus, Joules and Calibre; working for last 4+ years. Strong fundamentals on Physical design including...

Position: Physical Design Engineer with ASIC design Exp. Location: San Jose, CA (Onsite) Duration: Full-time Job Description: •BS/MS in Electrical Engineering or Computer Science •Minimum of hands-on experience in ASIC design and design constraints level synthesis, place and route, timing closure. •Standard PnR and signoff tools and their...

STA Physical Design Engineer LOCATION: San Jose, CA (hybrid 3 days onsite) DURATION: 6+ Months Description: Perform static timing analysis (STA) and timing optimization, generate and verifies timing constraints, performs SI/Noise analysis, and fixes timing & noise violations at full chip/block level for SoCs. - Strong understanding of digital design...

Position: Physical Design Engineer with ASIC design Exp. Location: San Jose, CA (Onsite) Duration: Full-time Job Description: BS/MS in Electrical Engineering or Computer Science Minimum of hands-on experience in ASIC design and design constraints level synthesis, place and route, timing closure. Standard PnR and signoff tools and their capabilities...

STA Physical Design EngineerLOCATION: San Jose, CA (hybrid 3 days onsite)DURATION: 6+ MonthsDescription:Perform static timing analysis (STA) and timing optimization, generate and verifies timing constraints, performs SI/Noise analysis, and fixes timing & noise violations at full chip/block level for SoCs.- Strong understanding of digital design concepts,...

STA Physical Design EngineerLOCATION: San Jose, CA (hybrid 3 days onsite)DURATION: 6+ MonthsDescription:Perform static timing analysis (STA) and timing optimization, generate and verifies timing constraints, performs SI/Noise analysis, and fixes timing & noise violations at full chip/block level for SoCs.- Strong understanding of digital design concepts,...

STA Physical Design EngineerLOCATION: San Jose, CA (hybrid 3 days onsite)DURATION: 6+ MonthsDescription:Perform static timing analysis (STA) and timing optimization, generate and verifies timing constraints, performs SI/Noise analysis, and fixes timing & noise violations at full chip/block level for SoCs.- Strong understanding of digital design concepts,...

Principal Application Engineer responsible for providing pre-sales and post-sales technical support for the Digital Implementation and Signoff tools. Will work closely with customers on bringing up flows at advanced nodes, and solving challenges in meeting power, performance and area (PPA) in vertical markets such as datacenter, ML/AI, networking and...

6 Months contract with possibility of extension Location - San Jose (Hybrid) Rate - $80 to $120 per hour Overview: Perform static timing analysis (STA) and timing optimization, generate and verifies timing constraints, performs SI/Noise analysis, and fixes timing & noise violations at full chip/block level for SoCs. Responsibilities: Strong understanding...

6 Months contract with possibility of extensionLocation - San Jose (Hybrid)Rate - $80 to $120 per hour Overview: Perform static timing analysis (STA) and timing optimization, generate and verifies timing constraints, performs SI/Noise analysis, and fixes timing & noise violations at full chip/block level for SoCs.Responsibilities:Strong understanding of...

6 Months contract with possibility of extensionLocation - San Jose (Hybrid)Rate - $80 to $120 per hour Overview: Perform static timing analysis (STA) and timing optimization, generate and verifies timing constraints, performs SI/Noise analysis, and fixes timing & noise violations at full chip/block level for SoCs.Responsibilities:Strong understanding of...

Synapse Design is looking forward to hire Design Verification Engineer expert. Experience:: +10 years Requirements: Solid programming skills in C/C++, Verilog, System Verilog, UVM, assembly, Perl/Python. Proficient in debugging complex SOC or CPU core designs involving multithreading, scheduling. Experience in triaging regressions, debugging, and resolving...