Physical Design STA Engineer

3 weeks ago


San Jose, United States Zenex Partners Full time

Physical Design STA Engineer

Location:- San Jose, CA (Hybrid Schedule)

Duration:- 6 Months

Pay rate:- $80 - $120/hr W2.


Responsibilities of Physical Design STA Engineer

  • Perform static timing analysis (STA) and timing optimization, generate and verifies timing constraints, performs SI/Noise analysis, and fixes timing & noise violations at full chip/block level for SoCs.


Requirements for Physical Design STA Engineer

  • Bachelor's degree.
  • Expert in Synopsys timing analysis tool Primetime.
  • Experience in timing ecos using Synopsys and other tools.
  • Familiarity with scripting languages like TCL, Perl, or Python for automation tasks.
  • Knowledge of ASIC design flow, including front-end and back-end processes.
  • Understanding of semiconductor fabrication processes and how they influence IC design.
  • Experience with low-power design techniques is a plus.
  • Knowledge of analog and mixed-signal design principles is beneficial for certain roles.



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