Senior Physical Design Engineer

Principal Application Engineer responsible for providing pre-sales and post-sales technical support for the Digital Implementation and Signoff tools. Will work closely with customers on bringing up flows at advanced nodes, and solving challenges in meeting power, performance and area (PPA) in vertical markets such as datacenter, ML/AI, networking and...

Technical/Functional Skills: BS/MS in Electrical Engineering or Computer Science 6+ year minimum of hands-on experience in ASIC design and design constraints level synthesis, place and route, timing closure. Standard PnR and signoff tools and their capabilities Understanding of basic power Analysis and power integrity Analysis Excellent English verbal...

Technical/FunctionalSkills: BS/MS in ElectricalEngineering or Computer Science 6+ year minimum ofhands-on experience in ASIC design and design constraints level synthesis, placeand route, timing closure. Standard PnR andsignoff tools and their capabilities Understanding of basicpower Analysis and power integrity Analysis Excellent Englishverbal and written...

Job DescriptionJob DescriptionPhysical Design STA EngineerLocation:- San Jose, CA (Hybrid Schedule)Duration:- 6 MonthsPay rate:- $80 - $120/hr W2.Responsibilities of Physical Design STA EngineerPerform static timing analysis (STA) and timing optimization, generate and verifies timing constraints, performs SI/Noise analysis, and fixes timing & noise...

Physical Design STA EngineerLocation:- San Jose, CA (Hybrid Schedule)Duration:- 6 MonthsPay rate:- $80 - $120/hr W2.Responsibilities of Physical Design STA EngineerPerform static timing analysis (STA) and timing optimization, generate and verifies timing constraints, performs SI/Noise analysis, and fixes timing & noise violations at full chip/block level for...

Physical Design STA EngineerLocation:- San Jose, CA (Hybrid Schedule)Duration:- 6 MonthsPay rate:- $80 - $120/hr W2.Responsibilities of Physical Design STA EngineerPerform static timing analysis (STA) and timing optimization, generate and verifies timing constraints, performs SI/Noise analysis, and fixes timing & noise violations at full chip/block level for...

Physical Design STA EngineerLocation:- San Jose, CA (Hybrid Schedule)Duration:- 6 MonthsPay rate:- $80 - $120/hr W2.Responsibilities of Physical Design STA EngineerPerform static timing analysis (STA) and timing optimization, generate and verifies timing constraints, performs SI/Noise analysis, and fixes timing & noise violations at full chip/block level for...

Trilyon, Inc. is looking for a Senior RTL Design Engineer for its direct client. If you have the skills and experience mentioned below, we would love to discuss it with you. Location: Onsite San Jose, CA Duration: 12 Plus Months JOB DUTIES: Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend System on Chip level...

Job Title: Physical Design Engineer Duration: 12 mos. + potential extension(s) and/or conversion Location: San Jose, CA Description: •Perform physical implementation in Synopsys tools (ICC2) •Develop and maintain the tool flow to support the project. •Work with Team to enhance PD methodology. •Fixing DRC/LVS issues •Fixing voltage drop...

Job Title:Sr Physical Design Engineer Location: San Jose, CA POSITION SUMMARY 7-10+ Yrs of experience in doing hands on physical design for complete flow of Netlist to GDSII Preferred Tool experience on Client ICC2, DC, PT, Calibre OR Genus, Innovus, Tempus, Joules and Calibre; working for last 4+ years. Strong fundamentals on Physical design including...

Cadence is the leader in hardware emulation-acceleration technologies and products. Looking for a hands-on Sr Principal Power/HW Design Engineer who wants to expand their scope, and grow their career. This position is located in our San Jose headquarter office, reports to the Engineering Group Director of R&D, and works in a growing talented organization....

Trilyon, Inc. is looking for a Senior RTL Design Engineer for its direct client. If you have the skills and experience mentioned below, we would love to discuss it with you. Location: Onsite San Jose, CA Duration: 12 Plus Months JOB DUTIES: Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend System on Chip level...

Trilyon, Inc. is looking for a Senior RTL Design Engineer for its direct client. If you have the skills and experience mentioned below, we would love to discuss it with you.Location: Onsite San Jose, CADuration: 12 Plus MonthsJOB DUTIES: Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend System on Chip level...

Acacia Communications designs intelligent transceivers using advanced signal processing and photonic integration for the 100G, 400G and 1T bit speed fiber optic transmission market deployed in data center, metro, long-haul and ultra-long haul telecommunication networks. What you'll do: You will be a key member of Acacia's Physical Design team working on next...

Job DescriptionThis is an opportunity to join a dynamic and growing team of engineers developing high-speed physical IP for industry-standard protocols. The successful candidate will be a highly self-motivated and results-oriented member of a small team of engineers that can learn and improve existing digital flows. The candidate will primarily be...

Job DescriptionThis is an opportunity to join a dynamic and growing team of engineers developing high-speed physical IP for industry-standard protocols. The successful candidate will be a highly self-motivated and results-oriented member of a small team of engineers that can learn and improve existing digital flows. The candidate will primarily be...

Trilyon, Inc. is looking for a Senior RTL Design Engineer for its direct client. If you have the skills and experience mentioned below, we would love to discuss it with you.Location: Onsite San Jose, CADuration: 12 Plus MonthsJOB DUTIES: Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend System on Chip level...

Trilyon, Inc. is looking for a Senior RTL Design Engineer for its direct client. If you have the skills and experience mentioned below, we would love to discuss it with you.Location: Onsite San Jose, CADuration: 12 Plus MonthsJOB DUTIES: Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend System on Chip level...

Trilyon, Inc. is looking for a Senior RTL Design Engineer for its direct client. If you have the skills and experience mentioned below, we would love to discuss it with you.Location: Onsite San Jose, CADuration: 12 Plus MonthsJOB DUTIES: Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend System on Chip level...

Position: Physical Design Engineer with ASIC design Exp. Location: San Jose, CA (Onsite) Duration: Full-time Job Description: •BS/MS in Electrical Engineering or Computer Science •Minimum of hands-on experience in ASIC design and design constraints level synthesis, place and route, timing closure. •Standard PnR and signoff tools and their...