Physical Design Engineer

At Sintegra Inc. we are seeking a skilled Physical Design Engineer to join our team in San Jose, CA. The ideal candidate will have a strong background in block-level design from RTL-to-GDSII, with expertise in synthesis, floor planning, place & route, timing/EMIR/PV closure, and signoff. The candidate should be proficient with the Cadence implementation tool...

At Sintegra Inc. we are seeking a skilled Physical Design Engineer to join our team in San Jose, CA. The ideal candidate will have a strong background in block-level design from RTL-to-GDSII, with expertise in synthesis, floor planning, place & route, timing/EMIR/PV closure, and signoff. The candidate should be proficient with the Cadence implementation tool...

At Sintegra Inc. we are seeking a skilled Physical Design Engineer to join our team in San Jose, CA. The ideal candidate will have a strong background in block-level design from RTL-to-GDSII, with expertise in synthesis, floor planning, place & route, timing/EMIR/PV closure, and signoff. The candidate should be proficient with the Cadence implementation tool...

At Sintegra Inc. we are seeking a skilled Physical Design Engineer to join our team in San Jose, CA. The ideal candidate will have a strong background in block-level design from RTL-to-GDSII, with expertise in synthesis, floor planning, place & route, timing/EMIR/PV closure, and signoff. The candidate should be proficient with the Cadence implementation tool...

Principal Application Engineer responsible for providing pre-sales and post-sales technical support for the Digital Implementation and Signoff tools. Will work closely with customers on bringing up flows at advanced nodes, and solving challenges in meeting power, performance and area (PPA) in vertical markets such as datacenter, ML/AI, networking and...

Do Something Wonderful! Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big i Design Engineer, Electrical Engineer, Computer Engineer, Computer Science, Design, Physical, Business...

Our client is a leading maker of ASIC technology for wireless infrastructure, cloud computing, machine learning, and networking. They develop advanced technologies in the industry in areas such as 2.5D and 3D interconnects. They are currently looking for a Physical Design Engineer who will have experience with physical layout skills to develop next...

Technical/FunctionalSkills: BS/MS in ElectricalEngineering or Computer Science 6+ year minimum ofhands-on experience in ASIC design and design constraints level synthesis, placeand route, timing closure. Standard PnR andsignoff tools and their capabilities Understanding of basicpower Analysis and power integrity Analysis Excellent Englishverbal and written...

Physical Design STA EngineerLocation:- San Jose, CA (Hybrid Schedule)Duration:- 6 MonthsPay rate:- $80 - $120/hr W2.Responsibilities of Physical Design STA EngineerPerform static timing analysis (STA) and timing optimization, generate and verifies timing constraints, performs SI/Noise analysis, and fixes timing & noise violations at full chip/block level for...

Physical Design STA EngineerLocation:- San Jose, CA (Hybrid Schedule)Duration:- 6 MonthsPay rate:- $80 - $120/hr W2.Responsibilities of Physical Design STA EngineerPerform static timing analysis (STA) and timing optimization, generate and verifies timing constraints, performs SI/Noise analysis, and fixes timing & noise violations at full chip/block level for...

Physical Design STA EngineerLocation:- San Jose, CA (Hybrid Schedule)Duration:- 6 MonthsPay rate:- $80 - $120/hr W2.Responsibilities of Physical Design STA EngineerPerform static timing analysis (STA) and timing optimization, generate and verifies timing constraints, performs SI/Noise analysis, and fixes timing & noise violations at full chip/block level for...

Technical/FunctionalSkills: BS/MS in ElectricalEngineering or Computer Science 6+ year minimum ofhands-on experience in ASIC design and design constraints level synthesis, placeand route, timing closure. Standard PnR andsignoff tools and their capabilities Understanding of basicpower Analysis and power integrity Analysis Excellent Englishverbal and written...

Synapse Design is looking forward to hire Design Verification Engineer expert. Experience:: +10 years Requirements: Solid programming skills in C/C++, Verilog, System Verilog, UVM, assembly, Perl/Python. Proficient in debugging complex SOC or CPU core designs involving multithreading, scheduling. Experience in triaging regressions, debugging, and resolving...

Synapse Design is looking forward to hire Design Verification Engineer expert. Experience:: +10 years Requirements: Solid programming skills in C/C++, Verilog, System Verilog, UVM, assembly, Perl/Python. Proficient in debugging complex SOC or CPU core designs involving multithreading, scheduling. Experience in triaging regressions, debugging, and resolving...

At Sintegra Inc. we are seeking a skilled Physical Design Engineer to join our team in San Jose, CA. The ideal candidate will have a strong background in block-level design from RTL-to-GDSII, with expertise in synthesis, floor planning, place & route, timing/EMIR/PV closure, and signoff. The candidate should be proficient with the Cadence implementation...

Job Description: ASIC Design & RTL SkillsArchitecture exploration and improvementsMicro-architecture development includes interface definition, state machine, data & control path definition, design partitioning.RTL development using Verilog, System VerilogLint, CDC, Synthesis, & Power OptimizationSoft and hard IP integrationCollaboration with verification...

JOB TITLE: STA Physical Design Engineer LOCATION: San Jose, CA (hybrid 3-4 days onsite) DURATION: 6+ Months PAY RANGE: $80-$110/hr TOP 3 SKILLS: - 8-10+ years' experience in Physical Design and STA - Expert in Synopsys timing analysis tool Primetime or similar tools.  - Experience in timing ecos using Synopsys and other tools. COMPANY: Our client, a...

Position: Physical Design Engineer Location: San Jose, CA / Austin, TX Job Description: Deep understanding of the concepts related to synthesis, place & route, CTS, timing convergence, IR/EM checks and signoff DRC/LVS closure. closely with the Design, DV, Implementation team to define low power vectors, generate early and signoff power data using PTPX or any...

Principal Application Engineer responsible for providing pre-sales and post-sales technical support for the Digital Implementation and Signoff tools. Will work closely with customers on bringing up flows at advanced nodes, and solving challenges in meeting power, performance and area (PPA) in vertical markets such as datacenter, ML/AI, networking and...

Job Details: Job Description: At Intel, we work every single day to design and manufacture silicon products as the fundamental building blocks that empower people's digital lives. Do you love contributing to flagship products in cutting edge process nodes? Do you love solving technical challenges that no one has solved yet? Do you enjoy working with...