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STA Physical Design Engineer

4 months ago


San Jose, United States Ursus, Inc. Full time

STA Physical Design Engineer

LOCATION: San Jose, CA (hybrid 3 days onsite)

DURATION: 6+ Months


Description:

Perform static timing analysis (STA) and timing optimization, generate and verifies timing constraints, performs SI/Noise analysis, and fixes timing & noise violations at full chip/block level for SoCs.


- Strong understanding of digital design concepts, including synthesis, timing analysis, and formal verification.

- Expert in Synopsys timing analysis tool Primetime, or similar tools.

- Experience in timing ecos using Synopsys and other tools.

- Familiarity with scripting languages like TCL, Perl, or Python for automation tasks.

- Knowledge of ASIC design flow, including front-end and back-end processes.


Requirements:

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.

- Understanding of semiconductor fabrication processes and how they influence IC design.



- Experience with low-power design techniques is a plus.

- Knowledge of analog and mixed-signal design principles is beneficial for certain roles.

- Willingness to stay updated on the latest advancements in semiconductor technology and design methodologies.