Physical Design Engineer
20 hours ago
We are seeking a highly skilled Physical Design Engineer to join our team at P. Chappel Associates Inc. in Santa Clara, California. This is a permanent position with a competitive salary range of $120K-$160K.
About the RoleThe successful candidate will be responsible for the entire product design lifecycle, working closely with frontend and integration teams to ensure successful tape outs. Key responsibilities include:
- Actively participating in technical and schedule discussions with customers, colleagues, and managers.
- Chip Level Floor planning, Placement, Clock Tree Synthesis, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, Power consumption Analysis, IR drop / Emig / DvD analysis, Physical Verification and Sign Off.
- Working with multiple P&R blocks to benchmark QOR.
To be successful in this role, you will need:
- BSEE. MSEE preferred.
- 5-10 years of experience in cutting-edge submicron physical design flows.
- Experience in Physical Design Implementation, including Floorplan, Chip Partitioning, Power mesh, Clock Tree, Physical optimization, Place and Route, STA, Timing closure, Power analysis, and Physical Verification.
- Experience in both Flat and Hierarchical layout.
- Experience with tape out designs in 28nm and 16nm/12nm technology nodes.
- Hands-on experience with ICC2 and Innovus.
- Calibre or ICV physical verification tool experience for DRC/LVS/ERC/ANT.
- Good understanding of ASIC Front-End Design.
- Good interpersonal and communication skills.
- Japanese language skills a plus.
P. Chappel Associates Inc is an established international company with a unique opportunity to join our North America expansion. We offer a dynamic work environment and the chance to work with exceptionally talented people.
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