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Physical Design Engineer Intern

2 months ago

Santa Clara, California, United States Ambarella Full time
About the Role

We are seeking a highly motivated Physical Design Engineer Intern to join our team at Ambarella. As a key member of our physical design team, you will play a critical role in the implementation and verification of our cutting-edge SoC for sub-28nm technology node.

Key Responsibilities
  • Support the physical design team with all aspects of physical design implementation, including floor-planning, auto place and route, physical implementation, timing verification, signal integrity analysis, power analysis, formal verification, and physical layout verification at block and/or full chip level.
  • Collaborate with the team to develop and implement hierarchical physical design strategies and methodologies.
  • Work with industry-leading EDA tools such as Cadence SoC Encounter, Synopsys ICC/Primetime, Magma Talus/Blast, and Mentor Calibre.
  • Develop and maintain a solid understanding of deep sub-micron technology issues and their impact on physical design.
Requirements
  • BS/MS in EE/computer science with prior internship experience in physical design.
  • Good understanding of VLSI digital design, layout, and timing closure.
  • Programming and scripting skills in C++, Perl, and TCL.
  • Basic knowledge of circuit design, device delays, and timing at gate-level.
  • Experience with UNIX and project work experience using industry-standard EDA tools.
Preferred Qualifications
  • Familiarity with hardware design languages such as Verilog and VHDL.
  • Experience with Cadence Encounter, RTL compiler, Conformal, and QRC.
  • Proven track record of delivering tape-out quality GDSII with silicon success.