Lead Engineer

2 weeks ago


San Diego, California, United States Synopsys Full time
Position Overview:

As a key member of the Synopsys team, you will play a vital role in the development of innovative System on Chip (SOC) solutions. We are seeking a talented Design Layout Implementation Engineer to contribute to our advanced packaging and multi-die design initiatives.

About Us:

At Synopsys, we are at the forefront of technological advancements that redefine industries. Our focus on safety, security, and reliability drives us to create dependable systems that power the future.

Role Responsibilities:

In this position, you will:
  • Engage in the development of SOCs, providing hands-on expertise and technical leadership to both internal and external SOC development teams.
  • Utilize cutting-edge place and route technologies to deliver comprehensive solutions, from architecture and design partitioning to floorplan, routing, and implementation.
  • Collaborate with a skilled team of thermal and electrical simulation engineers to optimize designs for performance and efficiency.
  • Drive the advancement of multi-die designs that support the latest innovations in GPUs and CPUs, while gaining insights into emerging technologies such as CoWoS, InFO, and 3DIC.

Key Qualifications:

The ideal candidate will possess:
  • A BSEE, MSEE, or PhD in Electrical or Computer Engineering.
  • A minimum of 5 years of experience in ASIC development, including expertise in digital place and route, floorplanning, clock tree synthesis, and low power techniques.
  • Experience in SOC-level architecture or SOC RTL development, or as a SOC chip engineer.
  • Familiarity with Synopsys EDA tools such as 3DIC Compiler, IC Compiler II, or Fusion Compiler.
  • Proficiency in IC Compiler and/or Fusion Compiler, with package layout experience being a significant advantage.

Preferred Experience:

Additional qualifications that would be beneficial include:
  • Experience with 2.5D/3D packaging and knowledge of CoWoS, InFo, and RDL.
  • Successful track record of multiple tapeouts in advanced nodes (16-/14-/10-/7-nm).
  • Custom layout experience for analog and RF.
  • Experience in chip-level thermal and EMIR analysis using tools like Redhawk.
  • Strong communication skills and experience in customer-centric environments.

Compensation and Benefits:

The base salary range for this role is competitive and commensurate with experience. Synopsys also offers a comprehensive benefits package, including health, wellness, and financial incentives.

Diversity and Inclusion:

At Synopsys, we value diversity and are committed to creating an inclusive environment for all employees. We welcome applicants from all backgrounds and experiences.

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