FPGA Soft IP Design Verification Lead Engineer
3 days ago
In the context of Intel's Programmable Solutions Group, this position plays a critical role in the development of high-speed protocol IP portfolios. As a Lead DV Engineer, you will be responsible for carrying out design validation for Intel's next-generation IP's across the FPGA IP product portfolios.
Key Responsibilities:- Create comprehensive verification and validation plans based on IP/FPGA architecture specifications and execute all IP validation tasks.
- Develop IP/subsystem/system-level testbenches, create tests, and establish necessary coverage goals based on specifications to verify implementation.
- Review verification and validation results against coverage goals, write, analyze, and achieve coverage metrics.
- Collaborate with cross-functional teams and prepare/support IP functional validation tests for IP bring-up on actual FPGA development kits to maximize FPGA hardware capability and improve IP quality and usability.
- Integrate Synopsys VIP and utilize it for end-to-end testing of Ethernet/MACSEC/IPSEC protocols.
- Develop verification and validation tools and flows as needed.
- Apply advanced techniques to achieve verification and validation with the highest quality, productivity, and time-to-market.
- Excellent communication skills.
- BS/MS in Electrical Engineering, Computer Engineering, or a closely related field of study plus 8 years of industry experience.
- 8+ years of experience developing verification collateral in Verilog, System Verilog, and UVM.
- 7 years of experience with Ethernet protocol verification.
- Fluency in UVM, with 7 years of prior work experience in complex coverage-driven random constraint UVM environments.
- Expertise in network security protocols: Ethernet/MACSEC/IPSEC end-to-end testing. Prefer candidates well-versed in PCIe and Memory security solutions.
- 7 years of experience creating test plans from high-level specifications and developing test cases.
- 7 years of experience in debugging skills to narrow down and isolate issues between RTL design and testbench or test case.
- 4+ years of leading complex projects and leadership experience working with cross-functional teams.
- Must have put together complex UVM environments from scratch.
- FPGA experience is a plus.
This role will be eligible for Intel's hybrid work model, allowing employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances, the work model may change to accommodate business needs.
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San Jose, California, United States Intel Full timeJob DescriptionAs a key member of the Intel Programmable Solutions Group, we are seeking a highly skilled FPGA Soft IP Design Verification Lead Engineer to join our team. This role will be responsible for leading the design verification and validation of Intel's next-generation IPs across the FPGA IP product portfolios.The successful candidate will have a...
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