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Senior ASIC Design Engineer

2 months ago

Sunnyvale, California, United States META Full time
Job Description

Meta is seeking a talented ASIC Design Engineer to join our Infrastructure organization. As a key member of our team, you will be responsible for designing and developing cutting-edge machine learning ASICs that deliver world-class inference and training performance.

Responsibilities
  • Explore and develop complex SoC and IP architectures
  • Develop micro-architectures and RTL designs using Verilog, System Verilog, and HLS
  • Optimize lints, CDC, synthesis, and power consumption
  • Collaborate with verification and emulation teams to develop test plans and debug
  • Work with implementation teams to close designs on timing and power
Requirements
  • 5+ years of experience in silicon development
  • Track record of first-pass success in ASIC development
  • Experience with Verilog or System Verilog
  • Experience in one of the following areas: micro-architecture and RTL development, SoC micro-architecture, design, and integration, or implementation and power methodology development
  • Experience working across multiple projects
  • Bachelor's degree in Computer Science, Computer Engineering, or relevant technical field
Preferred Qualifications
  • Experience in data path development
  • Experience in CPU, NOC, Memory, and Peripheral Subsystems
  • Experience with HLS, synthesis, timing closure, and formal verification methodology
  • Experience with power analysis and optimization
  • Experience with scripting languages (TCL, Python, Perl, Shell-scripting)

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Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity, or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.