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Senior ASIC Design Verification Engineer

1 month ago

Sunnyvale, California, United States Sql Pager LLC Full time
Job Description

We are seeking a highly skilled ASIC Design Verification Engineer to join our team at Sql Pager LLC. As a key member of our design team, you will be responsible for architecting and building a SoC-level and unit-level UVM verification environment.

Key Responsibilities:

  • Collaborate with Architecture and Design teams to verify the SoC features according to the chip use scenario.
  • Construct the chip level test plans, develop either directed or constrained random test vectors for closing the target coverage.
  • Participate evaluating and selecting third-party VIPs and integrate them into the test bench.
  • Debug test failures by collaborating with stakeholders to identify the root cause of the issues.
  • Develop and maintain the daily and weekly regressions.

Requirements:

  • A minimum of 10+ years of design verification experience with 1+ years of leader role (for Lead position).
  • Prior experience in developing a complete chip-level UVM test bench from scratch (for principal / Lead role).
  • Expert in coverage driven System verilog UVM with DPI-C, including UVM runtime phases (for Lead/Principal role).
  • Proficient in programming in C/C++, python and/or scripting language.
  • Prior experience in ASIC design verification.
  • In-depth knowledge in bus fabrics; NoC, AMBA etc in multi-CPU environment.

Preferred Qualifications:

  • Prior experience in verifying instruction driven designs like CPUs and GPGPUs.
  • Understanding of chip security, cold/warm boot sequences.
  • Experiences using SERDES based high speed interfaces, i.e. MIPI, PCIe and USB.
  • FPGA prototyping experience.
  • Knowledge in ISO-26262 ASIL compliances.

Education:

BSEE/BSCE required, Master in Science preferred.