Design Verification Engineer
4 hours ago
We are seeking a highly skilled Design Verification Engineer to join our team at Apple. As a key member of our silicon design group, you will be responsible for verifying high-throughput, complex cellular baseband modems and transceiver link controllers.
Key Responsibilities- Design and productize state-of-the-art cellular baseband modems and RF link controllers targeted for SOCs.
- Verify high-quality complex IPs and Sub-System designs by working closely with cross-functional teams.
- Develop re-usable verification environments to achieve quality goals.
- Collaborate with other product development groups across Apple to push the industry boundaries of what cellular systems can do.
- BS and 3+ years of relevant industry experience.
- Strong knowledge of System Verilog and UVM.
- Good understanding of System C, C/C++, Python/perl.
- Experience in developing and establishing DV Methodologies.
- Ability to develop System Verilog Testbench with UVM methodology from scratch.
- Education & Experience: BS and 3+ years of relevant industry experience.
Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.
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